Searched refs:cache_unroll (Results 1 - 10 of 10) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/
H A Dmips32_cache.h172 #define cache_unroll(base,op) \ macro
190 cache_unroll(start,Index_Writeback_Inv_D);
201 cache_unroll(start,Hit_Writeback_Inv_D);
216 cache_unroll(start,Index_Writeback_Inv_D);
228 cache_unroll(start,Index_Invalidate_I);
239 cache_unroll(start,Hit_Invalidate_I);
254 cache_unroll(start,Index_Invalidate_I);
266 cache_unroll(start,Index_Writeback_Inv_SD);
277 cache_unroll(start,Hit_Writeback_Inv_SD);
292 cache_unroll(star
[all...]
H A Dbcm4710_cache.h136 #define cache_unroll(base,op) \ macro
155 cache_unroll(start,Index_Writeback_Inv_D);
168 cache_unroll(start,Hit_Writeback_Inv_D);
184 cache_unroll(start,Index_Writeback_Inv_D);
196 cache_unroll(start,Index_Invalidate_I);
208 cache_unroll(start,Hit_Invalidate_I);
223 cache_unroll(start,Index_Invalidate_I);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips64/
H A Dmips64_cache.h149 #define cache_unroll(base,op) \ macro
165 cache_unroll(start,Index_Writeback_Inv_D);
176 cache_unroll(start,Hit_Writeback_Inv_D);
191 cache_unroll(start,Index_Writeback_Inv_D);
203 cache_unroll(start,Index_Invalidate_I);
214 cache_unroll(start,Hit_Invalidate_I);
229 cache_unroll(start,Index_Invalidate_I);
241 cache_unroll(start,Index_Writeback_Inv_SD);
252 cache_unroll(start,Hit_Writeback_Inv_SD);
267 cache_unroll(star
[all...]
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/
H A Dmips32_cache.h172 #define cache_unroll(base,op) \ macro
190 cache_unroll(start,Index_Writeback_Inv_D);
201 cache_unroll(start,Hit_Writeback_Inv_D);
216 cache_unroll(start,Index_Writeback_Inv_D);
228 cache_unroll(start,Index_Invalidate_I);
239 cache_unroll(start,Hit_Invalidate_I);
254 cache_unroll(start,Index_Invalidate_I);
266 cache_unroll(start,Index_Writeback_Inv_SD);
277 cache_unroll(start,Hit_Writeback_Inv_SD);
292 cache_unroll(star
[all...]
H A Dbcm4710_cache.h137 #define cache_unroll(base,op) \ macro
156 cache_unroll(start,Index_Writeback_Inv_D);
169 cache_unroll(start,Hit_Writeback_Inv_D);
185 cache_unroll(start,Index_Writeback_Inv_D);
197 cache_unroll(start,Index_Invalidate_I);
209 cache_unroll(start,Hit_Invalidate_I);
224 cache_unroll(start,Index_Invalidate_I);
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips64/
H A Dmips64_cache.h149 #define cache_unroll(base,op) \ macro
165 cache_unroll(start,Index_Writeback_Inv_D);
176 cache_unroll(start,Hit_Writeback_Inv_D);
191 cache_unroll(start,Index_Writeback_Inv_D);
203 cache_unroll(start,Index_Invalidate_I);
214 cache_unroll(start,Hit_Invalidate_I);
229 cache_unroll(start,Index_Invalidate_I);
241 cache_unroll(start,Index_Writeback_Inv_SD);
252 cache_unroll(start,Hit_Writeback_Inv_SD);
267 cache_unroll(star
[all...]
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/
H A Dmips32_cache.h172 #define cache_unroll(base,op) \ macro
190 cache_unroll(start,Index_Writeback_Inv_D);
201 cache_unroll(start,Hit_Writeback_Inv_D);
216 cache_unroll(start,Index_Writeback_Inv_D);
228 cache_unroll(start,Index_Invalidate_I);
239 cache_unroll(start,Hit_Invalidate_I);
254 cache_unroll(start,Index_Invalidate_I);
266 cache_unroll(start,Index_Writeback_Inv_SD);
277 cache_unroll(start,Hit_Writeback_Inv_SD);
292 cache_unroll(star
[all...]
H A Dbcm4710_cache.h136 #define cache_unroll(base,op) \ macro
155 cache_unroll(start,Index_Writeback_Inv_D);
168 cache_unroll(start,Hit_Writeback_Inv_D);
184 cache_unroll(start,Index_Writeback_Inv_D);
196 cache_unroll(start,Index_Invalidate_I);
208 cache_unroll(start,Hit_Invalidate_I);
223 cache_unroll(start,Index_Invalidate_I);
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/
H A Dmips32_cache.h172 #define cache_unroll(base,op) \ macro
190 cache_unroll(start,Index_Writeback_Inv_D);
201 cache_unroll(start,Hit_Writeback_Inv_D);
216 cache_unroll(start,Index_Writeback_Inv_D);
228 cache_unroll(start,Index_Invalidate_I);
239 cache_unroll(start,Hit_Invalidate_I);
254 cache_unroll(start,Index_Invalidate_I);
266 cache_unroll(start,Index_Writeback_Inv_SD);
277 cache_unroll(start,Hit_Writeback_Inv_SD);
292 cache_unroll(star
[all...]
H A Dbcm4710_cache.h137 #define cache_unroll(base,op) \ macro
156 cache_unroll(start,Index_Writeback_Inv_D);
169 cache_unroll(start,Hit_Writeback_Inv_D);
185 cache_unroll(start,Index_Writeback_Inv_D);
197 cache_unroll(start,Index_Invalidate_I);
209 cache_unroll(start,Hit_Invalidate_I);
224 cache_unroll(start,Index_Invalidate_I);

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