Searched refs:cache_op (Results 1 - 19 of 19) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/mm/
H A Dr5k-sc.c24 #define cache_op(base,op) \ macro
41 cache_op(start, R5K_Page_Invalidate_S);
62 cache_op(a, R5K_Page_Invalidate_S);
H A Dc-r4k.c1180 cache_op(Index_Store_Tag_I, begin);
1181 cache_op(Index_Store_Tag_D, begin);
1182 cache_op(Index_Store_Tag_SD, begin);
1188 cache_op(Index_Load_Tag_SD, addr);
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips64/mm/
H A Dr5k-sc.c24 #define cache_op(base,op) \ macro
41 cache_op(start, R5K_Page_Invalidate_S);
62 cache_op(a, R5K_Page_Invalidate_S);
H A Dc-r4k.c1184 cache_op(Index_Store_Tag_I, begin);
1185 cache_op(Index_Store_Tag_D, begin);
1186 cache_op(Index_Store_Tag_SD, begin);
1192 cache_op(Index_Load_Tag_SD, addr);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/
H A Dr4kcache.h17 #define cache_op(op,addr) \ macro
29 cache_op(Index_Invalidate_I, addr);
34 cache_op(Index_Writeback_Inv_D, addr);
39 cache_op(Index_Writeback_Inv_SD, addr);
44 cache_op(Hit_Invalidate_I, addr);
49 cache_op(Hit_Writeback_Inv_D, addr);
54 cache_op(Hit_Invalidate_D, addr);
59 cache_op(Hit_Invalidate_SD, addr);
64 cache_op(Hit_Writeback_Inv_SD, addr);
H A Dinst.h28 sdl_op, sdr_op, swr_op, cache_op, enumerator in enum:major_op
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips64/
H A Dr4kcache.h17 #define cache_op(op,addr) \ macro
29 cache_op(Index_Invalidate_I, addr);
34 cache_op(Index_Writeback_Inv_D, addr);
39 cache_op(Index_Writeback_Inv_SD, addr);
44 cache_op(Hit_Invalidate_I, addr);
49 cache_op(Hit_Writeback_Inv_D, addr);
54 cache_op(Hit_Invalidate_D, addr);
59 cache_op(Hit_Invalidate_SD, addr);
64 cache_op(Hit_Writeback_Inv_SD, addr);
H A Dinst.h28 sdl_op, sdr_op, swr_op, cache_op, enumerator in enum:major_op
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/
H A Dr4kcache.h17 #define cache_op(op,addr) \ macro
29 cache_op(Index_Invalidate_I, addr);
34 cache_op(Index_Writeback_Inv_D, addr);
39 cache_op(Index_Writeback_Inv_SD, addr);
44 cache_op(Hit_Invalidate_I, addr);
49 cache_op(Hit_Writeback_Inv_D, addr);
54 cache_op(Hit_Invalidate_D, addr);
59 cache_op(Hit_Invalidate_SD, addr);
64 cache_op(Hit_Writeback_Inv_SD, addr);
H A Dinst.h28 sdl_op, sdr_op, swr_op, cache_op, enumerator in enum:major_op
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips64/
H A Dr4kcache.h17 #define cache_op(op,addr) \ macro
29 cache_op(Index_Invalidate_I, addr);
34 cache_op(Index_Writeback_Inv_D, addr);
39 cache_op(Index_Writeback_Inv_SD, addr);
44 cache_op(Hit_Invalidate_I, addr);
49 cache_op(Hit_Writeback_Inv_D, addr);
54 cache_op(Hit_Invalidate_D, addr);
59 cache_op(Hit_Invalidate_SD, addr);
64 cache_op(Hit_Writeback_Inv_SD, addr);
H A Dinst.h28 sdl_op, sdr_op, swr_op, cache_op, enumerator in enum:major_op
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/
H A Dr4kcache.h17 #define cache_op(op,addr) \ macro
29 cache_op(Index_Invalidate_I, addr);
34 cache_op(Index_Writeback_Inv_D, addr);
39 cache_op(Index_Writeback_Inv_SD, addr);
44 cache_op(Hit_Invalidate_I, addr);
49 cache_op(Hit_Writeback_Inv_D, addr);
54 cache_op(Hit_Invalidate_D, addr);
59 cache_op(Hit_Invalidate_SD, addr);
64 cache_op(Hit_Writeback_Inv_SD, addr);
H A Dinst.h28 sdl_op, sdr_op, swr_op, cache_op, enumerator in enum:major_op
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/
H A Dr4kcache.h17 #define cache_op(op,addr) \ macro
29 cache_op(Index_Invalidate_I, addr);
34 cache_op(Index_Writeback_Inv_D, addr);
39 cache_op(Index_Writeback_Inv_SD, addr);
44 cache_op(Hit_Invalidate_I, addr);
49 cache_op(Hit_Writeback_Inv_D, addr);
54 cache_op(Hit_Invalidate_D, addr);
59 cache_op(Hit_Invalidate_SD, addr);
64 cache_op(Hit_Writeback_Inv_SD, addr);
H A Dinst.h28 sdl_op, sdr_op, swr_op, cache_op, enumerator in enum:major_op
/asus-wl-520gu-7.0.1.45/src/shared/
H A Dmin_osl.c82 cache_op(start, Index_Store_Tag_I);
92 cache_op(start, Index_Store_Tag_D);
114 cache_op(start, Index_Writeback_Inv_D);
128 cache_op(start, Index_Invalidate_I);
H A Dhndmips.c817 cache_op(start, Fill_I);
867 cache_op(dst + i, Fill_I);
979 cache_op(start, Fill_I);
/asus-wl-520gu-7.0.1.45/src/include/
H A Dmipsinc.h516 #define cache_op(base, op) \ macro

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