Searched refs:byteout (Results 1 - 23 of 23) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/isdn/hisax/
H A Davm_a1p.c57 #define byteout(addr,val) outb(val,addr) macro
71 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_REG_OFFSET+offset);
86 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_REG_OFFSET+offset);
87 byteout(cs->hw.avm.cfg_reg+DATAREG_OFFSET, value);
98 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_FIFO_OFFSET);
110 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_FIFO_OFFSET);
125 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,
141 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,
143 byteout(cs->hw.avm.cfg_reg+DATAREG_OFFSET, value);
154 byteout(c
[all...]
H A Dnj_u.c91 byteout(cs->hw.njet.base + NETJET_DMACTRL,
93 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0);
106 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
111 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
117 byteout(cs->hw.njet.auxa, 0);
118 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ);
119 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ);
120 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
201 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
207 byteout(c
[all...]
H A Dteleint.c24 #define byteout(addr,val) outb(val,addr) macro
36 byteout(ale, off);
57 byteout(ale, off);
80 byteout(ale, off);
89 byteout(adr, data);
101 byteout(ale, off);
110 byteout(adr, data[i]);
151 byteout(cs->hw.hfc.addr | 1, reg);
163 byteout(cs->hw.hfc.addr | 1, reg);
166 byteout(c
[all...]
H A Dnj_s.c91 byteout(cs->hw.njet.base + NETJET_DMACTRL,
93 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0);
106 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
111 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
117 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ);
118 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ);
119 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
207 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
213 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
223 byteout(c
[all...]
H A Dsaphir.c25 #define byteout(addr,val) outb(val,addr) macro
43 byteout(ale, off);
54 byteout(ale, off);
66 byteout(ale, off);
67 byteout(adr, data);
75 byteout(ale, off);
190 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, 0xff);
223 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val);
226 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 1);
229 byteout(c
[all...]
H A Dsportster.c25 #define byteout(addr,val) outb(val,addr) macro
64 byteout(calc_off(cs->hw.spt.isac, offset), value);
88 byteout(calc_off(cs->hw.spt.hscx[hscx], offset), value);
96 #define WRITEHSCX(cs, nr, reg, data) byteout(calc_off(cs->hw.spt.hscx[nr], reg), data)
141 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, 0);
154 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq);
160 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq);
179 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq);
H A Davm_a1.c27 #define byteout(addr,val) outb(val,addr) macro
39 byteout(adr + off, data);
116 byteout(cs->hw.avm.cfg_reg, 0x1E);
168 byteout(cs->hw.avm.cfg_reg, 0x16);
169 byteout(cs->hw.avm.cfg_reg, 0x1E);
273 byteout(cs->hw.avm.cfg_reg, 0x0);
276 byteout(cs->hw.avm.cfg_reg, 0x1);
278 byteout(cs->hw.avm.cfg_reg, 0x0);
283 byteout(cs->hw.avm.cfg_reg + 1, val);
285 byteout(c
[all...]
H A Dmic.c24 #define byteout(addr,val) outb(val,addr) macro
42 byteout(ale, off);
54 byteout(ale, off);
66 byteout(ale, off);
67 byteout(adr, data);
75 byteout(ale, off);
H A Dix1_micro.c31 #define byteout(addr,val) outb(val,addr) macro
51 byteout(ale, off);
62 byteout(ale, off);
74 byteout(ale, off);
75 byteout(adr, data);
83 byteout(ale, off);
196 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 1);
199 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 0);
H A Delsa.c47 #define byteout(addr,val) outb(val,addr) macro
153 byteout(ale, off);
164 byteout(ale, off);
176 byteout(ale, off);
177 byteout(adr, data);
185 byteout(ale, off);
261 byteout(cs->hw.elsa.ale, off);
274 byteout(cs->hw.elsa.ale, off);
275 byteout(cs->hw.elsa.itac, data);
366 byteout(c
[all...]
H A Dsedlbauer.c85 #define byteout(addr,val) outb(val,addr) macro
129 byteout(ale, off);
140 byteout(ale, off);
152 byteout(ale, off);
153 byteout(adr, data);
161 byteout(ale, off);
241 byteout(cs->hw.sedl.adr, offset);
252 byteout(cs->hw.sedl.adr, offset);
253 byteout(cs->hw.sedl.hscx, value);
449 byteout(c
[all...]
H A Dnetjet.h17 #define byteout(addr,val) outb(val,addr) macro
H A Dasuscom.c28 #define byteout(addr,val) outb(val,addr) macro
54 byteout(ale, off);
65 byteout(ale, off);
77 byteout(ale, off);
78 byteout(adr, data);
86 byteout(ale, off);
272 byteout(cs->hw.asus.adr, ASUS_RESET); /* Reset On */
280 byteout(cs->hw.asus.adr, 0); /* Reset Off */
H A Dteles3.c27 #define byteout(addr,val) outb(val,addr) macro
39 byteout(adr + off, data);
213 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg);
216 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg | 1);
221 byteout(cs->hw.teles3.cfg_reg, 0xff);
223 byteout(cs->hw.teles3.cfg_reg, 0x00);
229 byteout(cs->hw.teles3.isac + 0x3c, 0);
231 byteout(cs->hw.teles3.isac + 0x3c, 1);
H A Dniccy.c30 #define byteout(addr,val) outb(val,addr) macro
58 byteout(ale, off);
69 byteout(ale, off);
81 byteout(ale, off);
82 byteout(adr, data);
90 byteout(ale, off);
H A Disurf.c25 #define byteout(addr,val) outb(val,addr) macro
142 byteout(cs->hw.isurf.reset, chips); /* Reset On */
147 byteout(cs->hw.isurf.reset, ISURF_ISAR_EA); /* Reset Off */
H A Dnetjet.c43 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
58 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
59 byteout(cs->hw.njet.isac + ((offset & 0xf)<<2), value);
67 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
111 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
156 byteout(cs->hw.njet.base + NETJET_DMACTRL,
158 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0);
167 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
186 byteout(cs->hw.njet.base + NETJET_DMACTRL,
188 byteout(c
[all...]
H A Dgazel.c44 #define byteout(addr,val) outb(val,addr) macro
56 byteout(adr + off, data);
80 byteout(adr, off);
93 byteout(adr, off);
94 byteout(adr + 4, data);
102 byteout(adr, off);
109 byteout(adr, off);
H A Ddiva.c34 #define byteout(addr,val) outb(val,addr) macro
93 byteout(ale, off);
104 byteout(ale, off);
116 byteout(ale, off);
117 byteout(adr, data);
125 byteout(ale, off);
743 byteout(cs->hw.diva.ctrl, 0); /* LED off, Reset */
791 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
795 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
801 byteout(c
[all...]
H A Dteles0.c30 #define byteout(addr,val) outb(val,addr) macro
235 byteout(cs->hw.teles0.cfg_reg + 4, cfval);
237 byteout(cs->hw.teles0.cfg_reg + 4, cfval | 1);
H A Dhfc_sx.c57 #define byteout(addr,val) outb(val,addr) macro
69 byteout(cs->hw.hfcsx.base+1, regnum);
70 byteout(cs->hw.hfcsx.base, val);
81 byteout(cs->hw.hfcsx.base+1, regnum);
100 byteout(cs->hw.hfcsx.base+1, HFCSX_FIF_SEL);
101 byteout(cs->hw.hfcsx.base, fifo);
104 byteout(cs->hw.hfcsx.base, fifo);
120 byteout(cs->hw.hfcsx.base+1, HFCSX_CIRM);
121 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */
1540 byteout(c
[all...]
H A Dhfc_2bds0.c24 #define byteout(addr,val) outb(val,addr) macro
41 byteout(cs->hw.hfcD.addr | 1, reg);
58 byteout(cs->hw.hfcD.addr | 1, reg);
61 byteout(cs->hw.hfcD.addr, value);
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/isdn/hysdn/
H A Dboardergo.c29 #define byteout(addr,val) outb(val,addr) macro
145 byteout(card->iobase + PCI9050_INTR_REG, val);
147 byteout(card->iobase + PCI9050_USER_IO, PCI9050_E1_RESET); /* reset E1 processor */
247 byteout(card->iobase + PCI9050_USER_IO, PCI9050_E1_RUN); /* start E1 processor */
366 byteout(card->iobase + PCI9050_INTR_REG,

Completed in 99 milliseconds