Searched refs:MIPSInst (Results 1 - 6 of 6) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/
H A Dinst.h313 /* In case some other massaging is needed, keep MIPSInst as wrapper */
315 #define MIPSInst(x) x macro
318 #define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
321 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
324 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
327 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
330 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
331 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
334 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
337 #define MIPSInst_CACHESEL(x) ((MIPSInst(
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/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips64/
H A Dinst.h313 /* In case some other massaging is needed, keep MIPSInst as wrapper */
315 #define MIPSInst(x) x macro
318 #define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
321 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
324 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
327 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
330 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
331 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
334 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
337 #define MIPSInst_CACHESEL(x) ((MIPSInst(
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/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/
H A Dinst.h313 /* In case some other massaging is needed, keep MIPSInst as wrapper */
315 #define MIPSInst(x) x macro
318 #define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
321 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
324 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
327 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
330 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
331 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
334 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
337 #define MIPSInst_CACHESEL(x) ((MIPSInst(
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/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips64/
H A Dinst.h313 /* In case some other massaging is needed, keep MIPSInst as wrapper */
315 #define MIPSInst(x) x macro
318 #define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
321 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
324 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
327 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
330 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
331 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
334 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
337 #define MIPSInst_CACHESEL(x) ((MIPSInst(
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/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/
H A Dinst.h313 /* In case some other massaging is needed, keep MIPSInst as wrapper */
315 #define MIPSInst(x) x macro
318 #define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
321 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
324 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
327 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
330 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
331 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
334 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
337 #define MIPSInst_CACHESEL(x) ((MIPSInst(
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/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/
H A Dinst.h313 /* In case some other massaging is needed, keep MIPSInst as wrapper */
315 #define MIPSInst(x) x macro
318 #define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
321 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
324 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
327 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
330 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
331 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
334 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
337 #define MIPSInst_CACHESEL(x) ((MIPSInst(
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