Searched refs:Index_Writeback_Inv_D (Results 1 - 25 of 38) sorted by relevance

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/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/
H A Dcacheops.h17 #define Index_Writeback_Inv_D 0x01 macro
H A Dr4kcache.h34 cache_op(Index_Writeback_Inv_D, addr);
132 cache16_unroll32(start,Index_Writeback_Inv_D);
146 cache16_unroll32(start|way,Index_Writeback_Inv_D);
168 cache16_unroll32(start,Index_Writeback_Inv_D);
182 cache16_unroll32(start|way,Index_Writeback_Inv_D);
299 cache32_unroll32(start,Index_Writeback_Inv_D);
313 cache32_unroll32(start|way,Index_Writeback_Inv_D);
350 cache32_unroll32(start,Index_Writeback_Inv_D);
364 cache32_unroll32(start|way,Index_Writeback_Inv_D);
H A Dbcm4710_cache.h53 "i" (Index_Writeback_Inv_D));
155 cache_unroll(start,Index_Writeback_Inv_D);
184 cache_unroll(start,Index_Writeback_Inv_D);
H A Dmips32_cache.h44 "i" (Index_Writeback_Inv_D));
190 cache_unroll(start,Index_Writeback_Inv_D);
216 cache_unroll(start,Index_Writeback_Inv_D);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips64/
H A Dcacheops.h17 #define Index_Writeback_Inv_D 0x01 macro
H A Dr10kcacheops.h18 #define Index_Writeback_Inv_D 0x01 macro
H A Dr4kcache.h34 cache_op(Index_Writeback_Inv_D, addr);
132 cache16_unroll32(start,Index_Writeback_Inv_D);
146 cache16_unroll32(start|way,Index_Writeback_Inv_D);
168 cache16_unroll32(start,Index_Writeback_Inv_D);
182 cache16_unroll32(start|way,Index_Writeback_Inv_D);
299 cache32_unroll32(start,Index_Writeback_Inv_D);
313 cache32_unroll32(start|way,Index_Writeback_Inv_D);
350 cache32_unroll32(start,Index_Writeback_Inv_D);
364 cache32_unroll32(start|way,Index_Writeback_Inv_D);
H A Dr10kcache.h48 : "r" (addr), "i" (Index_Writeback_Inv_D));
187 cache32_unroll16(way0, Index_Writeback_Inv_D);
188 cache32_unroll16(way1, Index_Writeback_Inv_D);
212 cache32_unroll16(way0, Index_Writeback_Inv_D);
213 cache32_unroll16(way1, Index_Writeback_Inv_D);
H A Dmips64_cache.h40 "i" (Index_Writeback_Inv_D));
165 cache_unroll(start,Index_Writeback_Inv_D);
191 cache_unroll(start,Index_Writeback_Inv_D);
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/
H A Dcacheops.h17 #define Index_Writeback_Inv_D 0x01 macro
H A Dr4kcache.h34 cache_op(Index_Writeback_Inv_D, addr);
132 cache16_unroll32(start,Index_Writeback_Inv_D);
146 cache16_unroll32(start|way,Index_Writeback_Inv_D);
168 cache16_unroll32(start,Index_Writeback_Inv_D);
182 cache16_unroll32(start|way,Index_Writeback_Inv_D);
299 cache32_unroll32(start,Index_Writeback_Inv_D);
313 cache32_unroll32(start|way,Index_Writeback_Inv_D);
350 cache32_unroll32(start,Index_Writeback_Inv_D);
364 cache32_unroll32(start|way,Index_Writeback_Inv_D);
H A Dbcm4710_cache.h54 "i" (Index_Writeback_Inv_D));
156 cache_unroll(start,Index_Writeback_Inv_D);
185 cache_unroll(start,Index_Writeback_Inv_D);
H A Dmips32_cache.h44 "i" (Index_Writeback_Inv_D));
190 cache_unroll(start,Index_Writeback_Inv_D);
216 cache_unroll(start,Index_Writeback_Inv_D);
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips64/
H A Dcacheops.h17 #define Index_Writeback_Inv_D 0x01 macro
H A Dr10kcacheops.h18 #define Index_Writeback_Inv_D 0x01 macro
H A Dr4kcache.h34 cache_op(Index_Writeback_Inv_D, addr);
132 cache16_unroll32(start,Index_Writeback_Inv_D);
146 cache16_unroll32(start|way,Index_Writeback_Inv_D);
168 cache16_unroll32(start,Index_Writeback_Inv_D);
182 cache16_unroll32(start|way,Index_Writeback_Inv_D);
299 cache32_unroll32(start,Index_Writeback_Inv_D);
313 cache32_unroll32(start|way,Index_Writeback_Inv_D);
350 cache32_unroll32(start,Index_Writeback_Inv_D);
364 cache32_unroll32(start|way,Index_Writeback_Inv_D);
H A Dr10kcache.h48 : "r" (addr), "i" (Index_Writeback_Inv_D));
187 cache32_unroll16(way0, Index_Writeback_Inv_D);
188 cache32_unroll16(way1, Index_Writeback_Inv_D);
212 cache32_unroll16(way0, Index_Writeback_Inv_D);
213 cache32_unroll16(way1, Index_Writeback_Inv_D);
H A Dmips64_cache.h40 "i" (Index_Writeback_Inv_D));
165 cache_unroll(start,Index_Writeback_Inv_D);
191 cache_unroll(start,Index_Writeback_Inv_D);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/
H A Dcacheops.h17 #define Index_Writeback_Inv_D 0x01 macro
H A Dr4kcache.h34 cache_op(Index_Writeback_Inv_D, addr);
132 cache16_unroll32(start,Index_Writeback_Inv_D);
146 cache16_unroll32(start|way,Index_Writeback_Inv_D);
168 cache16_unroll32(start,Index_Writeback_Inv_D);
182 cache16_unroll32(start|way,Index_Writeback_Inv_D);
299 cache32_unroll32(start,Index_Writeback_Inv_D);
313 cache32_unroll32(start|way,Index_Writeback_Inv_D);
350 cache32_unroll32(start,Index_Writeback_Inv_D);
364 cache32_unroll32(start|way,Index_Writeback_Inv_D);
H A Dbcm4710_cache.h53 "i" (Index_Writeback_Inv_D));
155 cache_unroll(start,Index_Writeback_Inv_D);
184 cache_unroll(start,Index_Writeback_Inv_D);
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/
H A Dcacheops.h17 #define Index_Writeback_Inv_D 0x01 macro
H A Dr4kcache.h34 cache_op(Index_Writeback_Inv_D, addr);
132 cache16_unroll32(start,Index_Writeback_Inv_D);
146 cache16_unroll32(start|way,Index_Writeback_Inv_D);
168 cache16_unroll32(start,Index_Writeback_Inv_D);
182 cache16_unroll32(start|way,Index_Writeback_Inv_D);
299 cache32_unroll32(start,Index_Writeback_Inv_D);
313 cache32_unroll32(start|way,Index_Writeback_Inv_D);
350 cache32_unroll32(start,Index_Writeback_Inv_D);
364 cache32_unroll32(start|way,Index_Writeback_Inv_D);
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/mm/
H A Dc-r5432.c70 "i" (Index_Writeback_Inv_D));
181 cache32_unroll32(start,Index_Writeback_Inv_D);
182 cache32_unroll32(start+1,Index_Writeback_Inv_D);
204 cache32_unroll32(start,Index_Writeback_Inv_D);
205 cache32_unroll32(start+1,Index_Writeback_Inv_D);
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips64/mm/
H A Dc-sb1.c80 "r" (KSEG0), "i" (Index_Writeback_Inv_D));
109 "i" (Index_Writeback_Inv_D));
281 : "0" (addr), "i" (Index_Writeback_Inv_D), "i" (Index_Invalidate_I));

Completed in 195 milliseconds

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