Searched refs:Hit_Writeback_Inv_D (Results 1 - 25 of 34) sorted by relevance

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/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/
H A Dcacheops.h35 #define Hit_Writeback_Inv_D 0x15 macro
H A Dbcm4710_cache.h84 "i" (Hit_Writeback_Inv_D));
168 cache_unroll(start,Hit_Writeback_Inv_D);
H A Dmips32_cache.h95 "i" (Hit_Writeback_Inv_D));
201 cache_unroll(start,Hit_Writeback_Inv_D);
H A Dr4kcache.h49 cache_op(Hit_Writeback_Inv_D, addr);
157 cache16_unroll32(start,Hit_Writeback_Inv_D);
322 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
339 cache32_unroll32(start,Hit_Writeback_Inv_D);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips64/
H A Dcacheops.h35 #define Hit_Writeback_Inv_D 0x15 macro
H A Dr10kcacheops.h35 #define Hit_Writeback_Inv_D 0x15 macro
H A Dmips64_cache.h84 "i" (Hit_Writeback_Inv_D));
176 cache_unroll(start,Hit_Writeback_Inv_D);
H A Dr10kcache.h78 : "r" (addr), "i" (Hit_Writeback_Inv_D));
137 : "r" (addr), "i" (Hit_Writeback_Inv_D));
200 cache32_unroll32(start, Hit_Writeback_Inv_D);
H A Dr4kcache.h49 cache_op(Hit_Writeback_Inv_D, addr);
157 cache16_unroll32(start,Hit_Writeback_Inv_D);
322 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
339 cache32_unroll32(start,Hit_Writeback_Inv_D);
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/
H A Dcacheops.h35 #define Hit_Writeback_Inv_D 0x15 macro
H A Dbcm4710_cache.h85 "i" (Hit_Writeback_Inv_D));
169 cache_unroll(start,Hit_Writeback_Inv_D);
H A Dmips32_cache.h95 "i" (Hit_Writeback_Inv_D));
201 cache_unroll(start,Hit_Writeback_Inv_D);
H A Dr4kcache.h49 cache_op(Hit_Writeback_Inv_D, addr);
157 cache16_unroll32(start,Hit_Writeback_Inv_D);
322 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
339 cache32_unroll32(start,Hit_Writeback_Inv_D);
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips64/
H A Dcacheops.h35 #define Hit_Writeback_Inv_D 0x15 macro
H A Dr10kcacheops.h35 #define Hit_Writeback_Inv_D 0x15 macro
H A Dmips64_cache.h84 "i" (Hit_Writeback_Inv_D));
176 cache_unroll(start,Hit_Writeback_Inv_D);
H A Dr10kcache.h78 : "r" (addr), "i" (Hit_Writeback_Inv_D));
137 : "r" (addr), "i" (Hit_Writeback_Inv_D));
200 cache32_unroll32(start, Hit_Writeback_Inv_D);
H A Dr4kcache.h49 cache_op(Hit_Writeback_Inv_D, addr);
157 cache16_unroll32(start,Hit_Writeback_Inv_D);
322 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
339 cache32_unroll32(start,Hit_Writeback_Inv_D);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/
H A Dcacheops.h35 #define Hit_Writeback_Inv_D 0x15 macro
H A Dbcm4710_cache.h84 "i" (Hit_Writeback_Inv_D));
168 cache_unroll(start,Hit_Writeback_Inv_D);
H A Dmips32_cache.h95 "i" (Hit_Writeback_Inv_D));
201 cache_unroll(start,Hit_Writeback_Inv_D);
H A Dr4kcache.h49 cache_op(Hit_Writeback_Inv_D, addr);
157 cache16_unroll32(start,Hit_Writeback_Inv_D);
322 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
339 cache32_unroll32(start,Hit_Writeback_Inv_D);
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/
H A Dcacheops.h35 #define Hit_Writeback_Inv_D 0x15 macro
H A Dmips32_cache.h95 "i" (Hit_Writeback_Inv_D));
201 cache_unroll(start,Hit_Writeback_Inv_D);
H A Dbcm4710_cache.h85 "i" (Hit_Writeback_Inv_D));
169 cache_unroll(start,Hit_Writeback_Inv_D);

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