/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/ |
H A D | cacheops.h | 35 #define Hit_Writeback_Inv_D 0x15 macro
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H A D | bcm4710_cache.h | 84 "i" (Hit_Writeback_Inv_D)); 168 cache_unroll(start,Hit_Writeback_Inv_D);
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H A D | mips32_cache.h | 95 "i" (Hit_Writeback_Inv_D)); 201 cache_unroll(start,Hit_Writeback_Inv_D);
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H A D | r4kcache.h | 49 cache_op(Hit_Writeback_Inv_D, addr); 157 cache16_unroll32(start,Hit_Writeback_Inv_D); 322 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, 339 cache32_unroll32(start,Hit_Writeback_Inv_D);
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/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips64/ |
H A D | cacheops.h | 35 #define Hit_Writeback_Inv_D 0x15 macro
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H A D | r10kcacheops.h | 35 #define Hit_Writeback_Inv_D 0x15 macro
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H A D | mips64_cache.h | 84 "i" (Hit_Writeback_Inv_D)); 176 cache_unroll(start,Hit_Writeback_Inv_D);
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H A D | r10kcache.h | 78 : "r" (addr), "i" (Hit_Writeback_Inv_D)); 137 : "r" (addr), "i" (Hit_Writeback_Inv_D)); 200 cache32_unroll32(start, Hit_Writeback_Inv_D);
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H A D | r4kcache.h | 49 cache_op(Hit_Writeback_Inv_D, addr); 157 cache16_unroll32(start,Hit_Writeback_Inv_D); 322 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, 339 cache32_unroll32(start,Hit_Writeback_Inv_D);
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/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/ |
H A D | cacheops.h | 35 #define Hit_Writeback_Inv_D 0x15 macro
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H A D | bcm4710_cache.h | 85 "i" (Hit_Writeback_Inv_D)); 169 cache_unroll(start,Hit_Writeback_Inv_D);
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H A D | mips32_cache.h | 95 "i" (Hit_Writeback_Inv_D)); 201 cache_unroll(start,Hit_Writeback_Inv_D);
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H A D | r4kcache.h | 49 cache_op(Hit_Writeback_Inv_D, addr); 157 cache16_unroll32(start,Hit_Writeback_Inv_D); 322 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, 339 cache32_unroll32(start,Hit_Writeback_Inv_D);
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/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips64/ |
H A D | cacheops.h | 35 #define Hit_Writeback_Inv_D 0x15 macro
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H A D | r10kcacheops.h | 35 #define Hit_Writeback_Inv_D 0x15 macro
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H A D | mips64_cache.h | 84 "i" (Hit_Writeback_Inv_D)); 176 cache_unroll(start,Hit_Writeback_Inv_D);
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H A D | r10kcache.h | 78 : "r" (addr), "i" (Hit_Writeback_Inv_D)); 137 : "r" (addr), "i" (Hit_Writeback_Inv_D)); 200 cache32_unroll32(start, Hit_Writeback_Inv_D);
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H A D | r4kcache.h | 49 cache_op(Hit_Writeback_Inv_D, addr); 157 cache16_unroll32(start,Hit_Writeback_Inv_D); 322 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, 339 cache32_unroll32(start,Hit_Writeback_Inv_D);
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/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/ |
H A D | cacheops.h | 35 #define Hit_Writeback_Inv_D 0x15 macro
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H A D | bcm4710_cache.h | 84 "i" (Hit_Writeback_Inv_D)); 168 cache_unroll(start,Hit_Writeback_Inv_D);
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H A D | mips32_cache.h | 95 "i" (Hit_Writeback_Inv_D)); 201 cache_unroll(start,Hit_Writeback_Inv_D);
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H A D | r4kcache.h | 49 cache_op(Hit_Writeback_Inv_D, addr); 157 cache16_unroll32(start,Hit_Writeback_Inv_D); 322 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, 339 cache32_unroll32(start,Hit_Writeback_Inv_D);
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/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/ |
H A D | cacheops.h | 35 #define Hit_Writeback_Inv_D 0x15 macro
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H A D | mips32_cache.h | 95 "i" (Hit_Writeback_Inv_D)); 201 cache_unroll(start,Hit_Writeback_Inv_D);
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H A D | bcm4710_cache.h | 85 "i" (Hit_Writeback_Inv_D)); 169 cache_unroll(start,Hit_Writeback_Inv_D);
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