Searched refs:GT_REG_READ (Results 1 - 13 of 13) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/galileo-boards/ev64120/
H A Di2o.c33 GT_REG_READ(INBOUND_MESSAGE_REGISTER0_CPU_SIDE + 4 * messageRegNum,
55 GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, &regValue);
110 GT_REG_READ(OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, &regValue);
246 GT_REG_READ(INBOUND_DOORBELL_REGISTER_CPU_SIDE, &regData);
280 GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, &regData);
299 GT_REG_READ(OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, &regData);
431 GT_REG_READ(INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE,
437 GT_REG_READ(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, &qBar);
440 GT_REG_READ(QUEUE_CONTROL_REGISTER_CPU_SIDE, &cirQueSize);
466 GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SID
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H A Dcntmr.c43 GT_REG_READ(TIMER_COUNTER_CONTROL, &value);
80 GT_REG_READ(TIMER_COUNTER_CONTROL, &value);
83 GT_REG_READ(TIMER_COUNTER0 + 4 * countNum, &regValue);
103 GT_REG_READ(TIMER_COUNTER0 + countNum * 4, &value);
120 GT_REG_READ(TIMER_COUNTER_CONTROL, &value);
147 GT_REG_READ(TIMER_COUNTER_CONTROL, &value);
183 GT_REG_READ(TIMER_COUNTER_CONTROL, &value);
H A Ddma.c143 GT_REG_READ(CHANNEL0CONTROL + 4 * channel, &data);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/galileo-boards/evb64120A/
H A Dcntmr.h18 GT_REG_READ(CNTMR0, pData)
21 GT_REG_READ(CNTMR1, pData)
24 GT_REG_READ(CNTMR2, pData)
27 GT_REG_READ(CNTMR3, pData)
H A Dcore.h89 #define GT_REG_READ(offset, pData) \ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/galileo-boards/evb64120A/
H A Dcntmr.h18 GT_REG_READ(CNTMR0, pData)
21 GT_REG_READ(CNTMR1, pData)
24 GT_REG_READ(CNTMR2, pData)
27 GT_REG_READ(CNTMR3, pData)
H A Dcore.h89 #define GT_REG_READ(offset, pData) \ macro
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/galileo-boards/evb64120A/
H A Dcntmr.h18 GT_REG_READ(CNTMR0, pData)
21 GT_REG_READ(CNTMR1, pData)
24 GT_REG_READ(CNTMR2, pData)
27 GT_REG_READ(CNTMR3, pData)
H A Dcore.h89 #define GT_REG_READ(offset, pData) \ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/galileo-boards/evb64120A/
H A Dcntmr.h18 GT_REG_READ(CNTMR0, pData)
21 GT_REG_READ(CNTMR1, pData)
24 GT_REG_READ(CNTMR2, pData)
27 GT_REG_READ(CNTMR3, pData)
H A Dcore.h89 #define GT_REG_READ(offset, pData) \ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/galileo-boards/ev64120/compressed/
H A Dpci.c68 GT_REG_READ(INTERRUPT_CAUSE_REGISTER, &c18RegValue);
349 GT_REG_READ(HIGH_INTERRUPT_CAUSE_REGISTER, &c98RegValue);
680 GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
685 GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
732 GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
736 GT_REG_READ(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER,
839 GT_REG_READ(PCI_0MEMORY0_ADDRESS_REMAP, &pci0Mem1Base);
841 GT_REG_READ(PCI_0MEMORY1_ADDRESS_REMAP, &pci0Mem1Base);
844 GT_REG_READ(PCI_0MEMORY1_ADDRESS_REMAP, &pci0Mem1Base);
877 GT_REG_READ(PCI_0I_O_LOW_DECODE_ADDRES
[all...]
H A Dmemory.c35 GT_REG_READ((SCS_1_0_LOW_DECODE_ADDRESS + (bank / 2) * 0x10),
38 GT_REG_READ((SCS_0_LOW_DECODE_ADDRESS + bank * 8), &regBase);
54 GT_REG_READ((CS_2_0_LOW_DECODE_ADDRESS + (device / 3) * 0x10),
57 GT_REG_READ((CS_0_LOW_DECODE_ADDRESS + device * 0x8), &regBase);
73 GT_REG_READ((SCS_0_HIGH_DECODE_ADDRESS + bank * 8), &size);
75 GT_REG_READ((SCS_0_HIGH_DECODE_ADDRESS + bank * 8), &value);
93 GT_REG_READ((CS_0_HIGH_DECODE_ADDRESS + device * 8), &size);
95 GT_REG_READ((CS_0_HIGH_DECODE_ADDRESS + device * 8), &value);
117 GT_REG_READ(DEVICE_BANK0PARAMETERS + device * 4, &regValue);
527 GT_REG_READ((DEVICE_BANK0PARAMETER
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