Searched refs:GT_REG_READ (Results 1 - 13 of 13) sorted by relevance
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/galileo-boards/ev64120/ |
H A D | i2o.c | 33 GT_REG_READ(INBOUND_MESSAGE_REGISTER0_CPU_SIDE + 4 * messageRegNum, 55 GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, ®Value); 110 GT_REG_READ(OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, ®Value); 246 GT_REG_READ(INBOUND_DOORBELL_REGISTER_CPU_SIDE, ®Data); 280 GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, ®Data); 299 GT_REG_READ(OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, ®Data); 431 GT_REG_READ(INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE, 437 GT_REG_READ(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, &qBar); 440 GT_REG_READ(QUEUE_CONTROL_REGISTER_CPU_SIDE, &cirQueSize); 466 GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SID [all...] |
H A D | cntmr.c | 43 GT_REG_READ(TIMER_COUNTER_CONTROL, &value); 80 GT_REG_READ(TIMER_COUNTER_CONTROL, &value); 83 GT_REG_READ(TIMER_COUNTER0 + 4 * countNum, ®Value); 103 GT_REG_READ(TIMER_COUNTER0 + countNum * 4, &value); 120 GT_REG_READ(TIMER_COUNTER_CONTROL, &value); 147 GT_REG_READ(TIMER_COUNTER_CONTROL, &value); 183 GT_REG_READ(TIMER_COUNTER_CONTROL, &value);
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H A D | dma.c | 143 GT_REG_READ(CHANNEL0CONTROL + 4 * channel, &data);
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/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/galileo-boards/evb64120A/ |
H A D | cntmr.h | 18 GT_REG_READ(CNTMR0, pData) 21 GT_REG_READ(CNTMR1, pData) 24 GT_REG_READ(CNTMR2, pData) 27 GT_REG_READ(CNTMR3, pData)
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H A D | core.h | 89 #define GT_REG_READ(offset, pData) \ macro
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/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/galileo-boards/evb64120A/ |
H A D | cntmr.h | 18 GT_REG_READ(CNTMR0, pData) 21 GT_REG_READ(CNTMR1, pData) 24 GT_REG_READ(CNTMR2, pData) 27 GT_REG_READ(CNTMR3, pData)
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H A D | core.h | 89 #define GT_REG_READ(offset, pData) \ macro
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/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/galileo-boards/evb64120A/ |
H A D | cntmr.h | 18 GT_REG_READ(CNTMR0, pData) 21 GT_REG_READ(CNTMR1, pData) 24 GT_REG_READ(CNTMR2, pData) 27 GT_REG_READ(CNTMR3, pData)
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H A D | core.h | 89 #define GT_REG_READ(offset, pData) \ macro
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/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/galileo-boards/evb64120A/ |
H A D | cntmr.h | 18 GT_REG_READ(CNTMR0, pData) 21 GT_REG_READ(CNTMR1, pData) 24 GT_REG_READ(CNTMR2, pData) 27 GT_REG_READ(CNTMR3, pData)
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H A D | core.h | 89 #define GT_REG_READ(offset, pData) \ macro
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/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/galileo-boards/ev64120/compressed/ |
H A D | pci.c | 68 GT_REG_READ(INTERRUPT_CAUSE_REGISTER, &c18RegValue); 349 GT_REG_READ(HIGH_INTERRUPT_CAUSE_REGISTER, &c98RegValue); 680 GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, 685 GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, 732 GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, 736 GT_REG_READ(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER, 839 GT_REG_READ(PCI_0MEMORY0_ADDRESS_REMAP, &pci0Mem1Base); 841 GT_REG_READ(PCI_0MEMORY1_ADDRESS_REMAP, &pci0Mem1Base); 844 GT_REG_READ(PCI_0MEMORY1_ADDRESS_REMAP, &pci0Mem1Base); 877 GT_REG_READ(PCI_0I_O_LOW_DECODE_ADDRES [all...] |
H A D | memory.c | 35 GT_REG_READ((SCS_1_0_LOW_DECODE_ADDRESS + (bank / 2) * 0x10), 38 GT_REG_READ((SCS_0_LOW_DECODE_ADDRESS + bank * 8), ®Base); 54 GT_REG_READ((CS_2_0_LOW_DECODE_ADDRESS + (device / 3) * 0x10), 57 GT_REG_READ((CS_0_LOW_DECODE_ADDRESS + device * 0x8), ®Base); 73 GT_REG_READ((SCS_0_HIGH_DECODE_ADDRESS + bank * 8), &size); 75 GT_REG_READ((SCS_0_HIGH_DECODE_ADDRESS + bank * 8), &value); 93 GT_REG_READ((CS_0_HIGH_DECODE_ADDRESS + device * 8), &size); 95 GT_REG_READ((CS_0_HIGH_DECODE_ADDRESS + device * 8), &value); 117 GT_REG_READ(DEVICE_BANK0PARAMETERS + device * 4, ®Value); 527 GT_REG_READ((DEVICE_BANK0PARAMETER [all...] |
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