Searched refs:DDB_PCI_MEM_BASE (Results 1 - 13 of 13) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/ddb5xxx/ddb5074/
H A Dtime.c16 return *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr);
21 *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr)=data;
H A Dpci.c19 DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */
20 DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE -1,
H A Dsetup.c107 rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
140 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE , 0x10);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/ddb5xxx/
H A Dddb5074.h18 #define DDB_PCI_MEM_BASE 0x08000000 macro
21 #define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
H A Dddb5476.h33 #define DDB_PCI_MEM_BASE 0x08000000 macro
50 #define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/ddb5xxx/
H A Dddb5074.h18 #define DDB_PCI_MEM_BASE 0x08000000 macro
21 #define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
H A Dddb5476.h33 #define DDB_PCI_MEM_BASE 0x08000000 macro
50 #define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/ddb5xxx/
H A Dddb5074.h18 #define DDB_PCI_MEM_BASE 0x08000000 macro
21 #define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
H A Dddb5476.h33 #define DDB_PCI_MEM_BASE 0x08000000 macro
50 #define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/ddb5xxx/
H A Dddb5074.h18 #define DDB_PCI_MEM_BASE 0x08000000 macro
21 #define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
H A Dddb5476.h33 #define DDB_PCI_MEM_BASE 0x08000000 macro
50 #define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/ddb5xxx/ddb5476/
H A Dpci.c20 DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */
21 DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE -1,
H A Dsetup.c91 rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
241 ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
242 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
329 ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
330 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);

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