Searched refs:DDB_PCICTL0_L (Results 1 - 6 of 6) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/ddb5xxx/ddb5477/
H A Ddebug.c114 {"DDB_PCICTL0_L", DDB_BASE + DDB_PCICTL0_L},
H A Dsetup.c328 ddb_out32(DDB_PCICTL0_L, 0);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/ddb5xxx/
H A Dddb5477.h123 #define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/ddb5xxx/
H A Dddb5477.h123 #define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */ macro
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/ddb5xxx/
H A Dddb5477.h123 #define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/ddb5xxx/
H A Dddb5477.h123 #define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */ macro

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