Searched refs:DDB_INTPPES1 (Results 1 - 6 of 6) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/ddb5xxx/ddb5477/
H A Ddebug.c52 {"DDB_INTPPES1", DDB_BASE + DDB_INTPPES1},
H A Dirq.c46 #define PCI1 DDB_INTPPES1
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/ddb5xxx/
H A Dddb5477.h53 #define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/ddb5xxx/
H A Dddb5477.h53 #define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */ macro
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/ddb5xxx/
H A Dddb5477.h53 #define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/ddb5xxx/
H A Dddb5477.h53 #define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */ macro

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