Searched refs:DDB_INTPPES0 (Results 1 - 6 of 6) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/ddb5xxx/ddb5477/
H A Ddebug.c51 {"DDB_INTPPES0", DDB_BASE + DDB_INTPPES0},
H A Dirq.c45 #define PCI0 DDB_INTPPES0
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/ddb5xxx/
H A Dddb5477.h52 #define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/ddb5xxx/
H A Dddb5477.h52 #define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */ macro
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/ddb5xxx/
H A Dddb5477.h52 #define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/ddb5xxx/
H A Dddb5477.h52 #define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */ macro

Completed in 88 milliseconds