Searched refs:DDB_INTCTRL0 (Results 1 - 7 of 7) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/ddb5xxx/ddb5477/
H A Dirq_5477.c130 reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
147 reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
163 reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
H A Ddebug.c41 {"DDB_INTCTRL0", DDB_BASE + DDB_INTCTRL0},
H A Dirq.c88 ddb_out32(DDB_INTCTRL0, 0);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/ddb5xxx/
H A Dddb5477.h38 #define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/ddb5xxx/
H A Dddb5477.h38 #define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */ macro
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/ddb5xxx/
H A Dddb5477.h38 #define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/ddb5xxx/
H A Dddb5477.h38 #define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */ macro

Completed in 46 milliseconds