Searched refs:DCACHELINESIZE (Results 1 - 5 of 5) sorted by relevance
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/arm/mm/ |
H A D | proc-arm920.S | 45 #define DCACHELINESIZE 32 define 190 bic r0, r0, #DCACHELINESIZE - 1 @ && added by PGM 191 bic r1, r1, #DCACHELINESIZE - 1 @ && added by DHM 199 add r0, r0, #DCACHELINESIZE 202 add r0, r0, #DCACHELINESIZE 206 add r0, r0, #DCACHELINESIZE 209 add r0, r0, #DCACHELINESIZE 229 add r0, r0, #DCACHELINESIZE 231 add r0, r0, #DCACHELINESIZE 234 add r0, r0, #DCACHELINESIZE [all...] |
H A D | proc-arm922.S | 46 #define DCACHELINESIZE 32 define 186 bic r0, r0, #DCACHELINESIZE - 1 @ && added by PGM 187 bic r1, r1, #DCACHELINESIZE - 1 @ && added by DHM 195 add r0, r0, #DCACHELINESIZE 198 add r0, r0, #DCACHELINESIZE 202 add r0, r0, #DCACHELINESIZE 205 add r0, r0, #DCACHELINESIZE 225 add r0, r0, #DCACHELINESIZE 227 add r0, r0, #DCACHELINESIZE 230 add r0, r0, #DCACHELINESIZE [all...] |
H A D | proc-arm926.S | 45 #define DCACHELINESIZE 32 define 199 bic r0, r0, #DCACHELINESIZE - 1 @ && added by PGM 208 add r0, r0, #DCACHELINESIZE 211 add r0, r0, #DCACHELINESIZE 215 add r0, r0, #DCACHELINESIZE 218 add r0, r0, #DCACHELINESIZE 240 add r0, r0, #DCACHELINESIZE 242 add r0, r0, #DCACHELINESIZE 245 add r0, r0, #DCACHELINESIZE 247 add r0, r0, #DCACHELINESIZE [all...] |
H A D | proc-sa110.S | 34 #define DCACHELINESIZE 32 define 45 1001: ldr \rd, [\ra], #DCACHELINESIZE 52 1001: ldr \rd, [\ra], #DCACHELINESIZE 58 1002: ldr \rd, [\ra], #DCACHELINESIZE 276 bic r0, r0, #DCACHELINESIZE - 1 282 add r0, r0, #DCACHELINESIZE 285 add r0, r0, #DCACHELINESIZE 311 add r0, r0, #DCACHELINESIZE 313 add r0, r0, #DCACHELINESIZE 314 subs r1, r1, #2 * DCACHELINESIZE [all...] |
H A D | proc-arm1020.S | 45 #define DCACHELINESIZE 32 define 201 bic r0, r0, #DCACHELINESIZE - 1 209 add r0, r0, #DCACHELINESIZE 215 add r0, r0, #DCACHELINESIZE 245 add r0, r0, #DCACHELINESIZE 252 subs r1, r1, #2 * DCACHELINESIZE 280 tst r0, #DCACHELINESIZE - 1 281 bic r0, r0, #DCACHELINESIZE - 1 289 tst r1, #DCACHELINESIZE - 1 303 add r0, r0, #DCACHELINESIZE [all...] |
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