Searched refs:CSR0_STRT (Results 1 - 11 of 11) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/net/
H A Dni65.h33 #define CSR0_STRT 0x0002 /* Start (RS) */ macro
H A Dsk_g16.h65 #define CSR0_STRT 0x0002 /* Start (RS) */ macro
H A Dam79c961a.h32 #define CSR0_STRT 0x0002 macro
H A Dsun3lance.c219 #define CSR0_STRT 0x0002 /* start (RS) */ macro
430 DREG = CSR0_IDON | CSR0_STRT | CSR0_INEA;
545 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT;
578 REGA( CSR0 ) = CSR0_INIT | CSR0_STRT;
609 REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT;
695 REGA(CSR0) = CSR0_STRT | CSR0_INEA;
733 REGA(CSR0) = CSR0_STRT | CSR0_INEA;
908 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT;
H A Datarilance.c21 following AMD, CSR0_STRT should be set only after IDON is detected
319 #define CSR0_STRT 0x0002 /* start (RS) */ macro
672 DREG = CSR0_STRT;
768 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT;
870 DREG = csr0 & ~(CSR0_INIT | CSR0_STRT | CSR0_STOP |
905 DREG = CSR0_STRT;
942 DREG = CSR0_STRT;
1122 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT;
H A Dbagetlance.c307 #define CSR0_STRT 0x0002 /* start (RS) */ macro
760 DREG = CSR0_STRT;
872 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT;
995 DREG = csr0 & ~(CSR0_INIT | CSR0_STRT | CSR0_STOP |
1037 DREG = CSR0_STRT;
1074 DREG = CSR0_STRT;
1285 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT;
H A Dsk_mca.h100 #define CSR0_STRT 0x0002 /* start LANCE */ macro
H A Dni65.c678 writedatareg(CSR0_STRT | csr0);
700 writedatareg(CSR0_STRT | csr0);
775 writedatareg(CSR0_CLRALL | CSR0_INEA | CSR0_STRT);
H A Dam79c961a.c257 write_rreg (dev->base_addr, CSR0, CSR0_IENA|CSR0_STRT);
H A Dsk_g16.c1222 SK_write_reg(CSR0, CSR0_IDON | CSR0_INEA | CSR0_STRT);
H A Dsk_mca.c582 SetLANCE(dev, LANCE_CSR0, oldcsr0 | CSR0_IDON | CSR0_STRT);

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