/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/net/ |
H A D | sk_g16.c | 275 * CSR0 - Status and Control flags 284 #define CSR0 0x00 macro 936 PRINTK(("## %s: At beginning of SK_open(). CSR0: %#06x\n", 937 SK_NAME, SK_read_reg(CSR0))); 1035 printk("## %s: After lance init. CSR0: %#06x\n", 1036 SK_NAME, SK_read_reg(CSR0)); 1037 SK_write_reg(CSR0, CSR0_STOP); 1038 printk("## %s: LANCE stopped. CSR0: %#06x\n", 1039 SK_NAME, SK_read_reg(CSR0)); 1041 printk("## %s: Reinit with DTX + DRX off. CSR0 [all...] |
H A D | sun3lance.c | 209 #define CSR0 0 /* mode/status */ macro 216 /* CSR0 */ 322 ioaddr_probe[1] = CSR0; 345 REGA(CSR0) = CSR0_STOP; 412 REGA(CSR0) = CSR0_STOP; 416 /* From now on, AREG is kept to point to CSR0 */ 417 REGA(CSR0) = CSR0_INIT; 545 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT; 568 AREG = CSR0; 576 REGA( CSR0 ) [all...] |
H A D | am79c961a.c | 199 write_rreg (dev->base_addr, CSR0, CSR0_BABL|CSR0_CERR|CSR0_MISS|CSR0_MERR|CSR0_TINT|CSR0_RINT|CSR0_STOP); 255 write_rreg (dev->base_addr, CSR0, CSR0_STOP); 257 write_rreg (dev->base_addr, CSR0, CSR0_IENA|CSR0_STRT); 294 write_rreg (dev->base_addr, CSR0, CSR0_STOP); 354 stopped = read_rreg(dev->base_addr, CSR0) & CSR0_STOP; 430 write_rreg (dev->base_addr, CSR0, CSR0_TDMD|CSR0_IENA); 561 status = read_rreg(dev->base_addr, CSR0); 562 write_rreg(dev->base_addr, CSR0, status & (CSR0_TINT|CSR0_RINT|CSR0_MISS|CSR0_IENA)); 582 write_rreg (dev->base_addr, CSR0, CSR0_STOP);
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H A D | am79c961a.h | 30 #define CSR0 0 macro
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H A D | ariadne.c | 232 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 316 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 370 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 392 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 412 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 499 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 555 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 678 lance->RAP = CSR0; /* PCnet-ISA Controller Status */ 702 lance->RAP = CSR0; /* PCnet-ISA Controller Status */
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H A D | atarilance.c | 20 optimized register access (keep AREG pointing to CSR0) 309 #define CSR0 0 /* mode/status */ macro 316 /* CSR0 */ 495 PROBE_PRINT(( "lance_probe1: testing CSR0 register function (1)\n" )); 497 ioaddr[1] = CSR0; 504 PROBE_PRINT(( "lance_probe1: testing CSR0 register function (2)\n" )); 532 REGA( CSR0 ) = CSR0_STOP; 658 REGA( CSR0 ) = CSR0_INIT; 659 /* From now on, AREG is kept to point to CSR0 */ 738 AREG = CSR0; [all...] |
H A D | bagetlance.c | 297 #define CSR0 0 /* mode/status */ macro 304 /* CSR0 */ 563 PROBE_PRINT(( "lance_probe1: testing CSR0 register function (1)\n" )); 565 ioaddr[1] = CSR0; 572 PROBE_PRINT(( "lance_probe1: testing CSR0 register function (2)\n" )); 600 REGA( CSR0 ) = CSR0_STOP; 746 REGA( CSR0 ) = CSR0_INIT; 747 /* From now on, AREG is kept to point to CSR0 */ 843 AREG = CSR0; 872 REGA( CSR0 ) [all...] |
H A D | depca.h | 25 #define CSR0 0 macro 46 ** Control and Status Register 0 (CSR0) bit definitions
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H A D | ni65.c | 146 #define CSR0 0x00 macro 156 #define writedatareg(val) { writereg(val,CSR0); } 226 writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */ 241 outw(CSR0,PORT+L_ADDRREG); /* switch back to CSR0 */ 369 if( (j=readreg(CSR0)) != 0x4) { 418 if(readreg(CSR0) & CSR0_IDON) 437 writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */ 483 writereg(CSR0_CLRALL|CSR0_STOP,CSR0); 499 writereg(CSR0_INIT,CSR0); /* thi [all...] |
H A D | depca.c | 493 outw(CSR0, DEPCA_ADDR);\ 783 outw(CSR0, DEPCA_ADDR); 790 printk("CSR0: 0x%4.4x\n", inw(DEPCA_DATA)); 873 outw(CSR0, DEPCA_ADDR); 913 outw(CSR0, DEPCA_ADDR); 1061 outw(CSR0, DEPCA_ADDR); 1085 outw(CSR0, DEPCA_ADDR); 1125 outw(CSR0, DEPCA_ADDR); /* Point back to CSR0 */ 1139 outw(CSR0, DEPCA_ADD [all...] |
H A D | ariadne.h | 62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */ macro 174 * Bit definitions for CSR0 (PCnet-ISA Controller Status)
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/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/net/wan/ |
H A D | sbni.c | 325 outb( 0, ioaddr + CSR0 ); 329 outb( EN_INT | TR_REQ, ioaddr + CSR0 ); 332 outb( 0, ioaddr + CSR0 ); 374 if( inb( ioaddr + CSR0 ) & 0x01 ) 488 if( inb( dev->base_addr + CSR0 ) & (RC_RDY | TR_RDY) ) 492 (inb( nl->second->base_addr+CSR0 ) & (RC_RDY | TR_RDY)) ) 518 outb( (inb( ioaddr + CSR0 ) & ~EN_INT) | TR_REQ, ioaddr + CSR0 ); 522 csr0 = inb( ioaddr + CSR0 ); 535 csr0 = inb( ioaddr + CSR0 ); 544 outb( inb( ioaddr + CSR0 ) & ~TR_REQ, ioaddr + CSR0 ); local 547 outb( inb( ioaddr + CSR0 ) | EN_INT, ioaddr + CSR0 ); local 581 outb( inb( ioaddr + CSR0 ) ^ CT_ZER, ioaddr + CSR0 ); local [all...] |
H A D | sbni.h | 26 CSR0 = 0, enumerator in enum:sbni_reg 31 /* CSR0 mapping */
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/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/net/pcmcia/ |
H A D | xircom_cb.c | 55 #define CSR0 0x00 macro 103 CSR0, CSR6, CSR7, CSR9, CSR10, CSR15 521 val = inl(card->io_port + CSR0); 523 outl(val, card->io_port + CSR0); 527 val = inl(card->io_port + CSR0); 529 outl(val, card->io_port + CSR0); 534 outl(val, card->io_port + CSR0);
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H A D | xircom_tulip_cb.c | 217 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, enumerator in enum:xircom_offsets 324 unsigned int csr0; /* CSR0 setting. */ 508 outl(SoftwareReset, ioaddr + CSR0); 512 outl(tp->csr0, ioaddr + CSR0); 788 printk(KERN_DEBUG "%s: Done xircom_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n", 789 dev->name, inl(ioaddr + CSR0), inl(ioaddr + CSR5),
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/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/net/tulip/ |
H A D | tulip.h | 104 CSR0 = 0, enumerator in enum:tulip_offsets 376 unsigned int csr0; /* CSR0 setting. */
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H A D | tulip_core.c | 301 outl(0x00000001, ioaddr + CSR0); 307 outl(tp->csr0, ioaddr + CSR0); 488 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n", 489 dev->name, inl(ioaddr + CSR0), inl(ioaddr + CSR5),
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