Searched refs:CCR2 (Results 1 - 2 of 2) sorted by relevance
| /asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/net/wan/ |
| H A D | dscc4.c | 228 #define CCR2 0x10 macro
766 writel(0x00050008 & ~RxActivate, ioaddr + CCR2);
782 * power-down mode or..." and CCR2.RAC = 1 are two different
886 writel(0x00050000, ioaddr + SCC_REG_START(dev_id) + CCR2);
1324 writel(0x08050008, scc_offset + CCR2);
1457 writel(readl(scc_offset + CCR2) & ~RxActivate,
1458 scc_offset + CCR2); local
1509 writel(readl(scc_offset + CCR2) | RxActivate,
1510 scc_offset + CCR2); local
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| /asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/char/pcmcia/ |
| H A D | synclink_cs.c | 298 #define CCR2 0x2e macro
3381 * BGR[9..8] contained in CCR2[7..6]
3388 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
3390 write_reg(info, (unsigned char) (channel + CCR2), val);
3444 /* CCR2 (Channel B)
3457 write_reg(info, CHB + CCR2, 0x38);
3459 write_reg(info, CHB + CCR2, 0x30);
3491 /* CCR2:04 SSEL Clock source select, 1=submode b */
3492 val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
3493 write_reg(info, CHA + CCR2, va
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