Searched refs:reg_name (Results 76 - 100 of 290) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c101 #define SR(reg_name)\
102 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
103 mm ## reg_name
105 #define SRI(reg_name, block, id)\
106 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
107 mm ## block ## id ## _ ## reg_name
109 #define SRIR(var_name, reg_name, block, id)\
110 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_ID
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c201 #define SRI(reg_name, block, id)\
202 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
203 reg ## block ## id ## _ ## reg_name
205 #define SRI_DMUB(reg_name)\
206 BASE(reg ## reg_name ## _BASE_IDX) + \
207 reg ## reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn35/
H A Dirq_service_dcn35.c199 #define SRI(reg_name, block, id)\
200 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
201 reg ## block ## id ## _ ## reg_name
203 #define SRI_DMUB(reg_name)\
204 BASE(reg ## reg_name ## _BASE_IDX) + \
205 reg ## reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c207 #define SRI(reg_name, block, id)\
208 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
209 reg ## block ## id ## _ ## reg_name
211 #define SRI_DMUB(reg_name)\
212 BASE(reg ## reg_name ## _BASE_IDX) + \
213 reg ## reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c187 #define SRI(reg_name, block, id)\
188 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
189 mm ## block ## id ## _ ## reg_name
191 #define SRI_DMUB(reg_name)\
192 BASE(mm ## reg_name ## _BASE_IDX) + \
193 mm ## reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c212 #define SRI(reg_name, block, id)\
213 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
214 mm ## block ## id ## _ ## reg_name
216 #define SRI_DMUB(reg_name)\
217 BASE(mm ## reg_name ## _BASE_IDX) + \
218 mm ## reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c200 #define SRI(reg_name, block, id)\
201 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
202 reg ## block ## id ## _ ## reg_name
204 #define SRI_DMUB(reg_name)\
205 BASE(reg ## reg_name ## _BASE_IDX) + \
206 reg ## reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c202 #define SRI(reg_name, block, id)\
203 (BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
204 reg ## block ## id ## _ ## reg_name)
206 #define SRI_DMUB(reg_name)\
207 (BASE(reg ## reg_name ## _BASE_IDX) + \
208 reg ## reg_name)
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c205 #define SRI(reg_name, block, id)\
206 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
207 mm ## block ## id ## _ ## reg_name
209 #define SRI_DMUB(reg_name)\
210 BASE(mm ## reg_name ## _BASE_IDX) + \
211 mm ## reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c178 #define SRI(reg_name, block, id)\
179 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
180 reg ## block ## id ## _ ## reg_name
182 #define SRI_DMUB(reg_name)\
183 BASE(reg ## reg_name ## _BASE_IDX) + \
184 reg ## reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c129 #define SR(reg_name)\
130 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
131 reg ## reg_name
133 #define SRI(reg_name, block, id)\
134 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 reg ## block ## id ## _ ## reg_name
137 #define SRI2(reg_name, block, id)\
138 .reg_name
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/linux-master/drivers/crypto/cavium/zip/
H A Dzip_main.h67 char *reg_name; member in struct:zip_registers
/linux-master/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_dccg.c37 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dccg.c37 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_vpg.c39 #define FN(reg_name, field_name) \
H A Ddcn31_afmt.c40 #define FN(reg_name, field_name) \
H A Ddcn31_apg.c39 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_dccg.c38 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_ipp.c34 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hpo_dp_link_encoder.c38 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_dccg.c38 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_vmid.c38 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce120/
H A Ddce120_resource.c136 #define SR(reg_name)\
137 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
138 mm ## reg_name
140 #define SRI(reg_name, block, id)\
141 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 mm ## block ## id ## _ ## reg_name
151 #define MMHUB_SR(reg_name)\
152 .reg_name
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/linux-master/drivers/cpufreq/
H A Dcpufreq-dt.c196 const char *reg_name[] = { NULL, NULL }; local
221 reg_name[0] = find_supply_name(cpu_dev);
222 if (reg_name[0]) {
223 priv->opp_token = dev_pm_opp_set_regulators(cpu_dev, reg_name);
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15_common.h58 #define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val) \
59 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
61 adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
63 ~REG_FIELD_MASK(reg_name, field)) | (val) << REG_FIELD_SHIFT(reg_name, field), \

Completed in 282 milliseconds

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