/linux-master/arch/mips/bmips/ |
H A D | dma.c | 25 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
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/linux-master/arch/sh/mm/ |
H A D | tlb-urb.c | 43 __raw_writel(status, MMUCR); 55 __raw_writel(status, MMUCR); 89 __raw_writel(status, MMUCR);
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H A D | cache-j2.c | 31 __raw_writel(CACHE_ENABLE | ICACHE_FLUSH, j2_ccr_base + cpu); 38 __raw_writel(CACHE_ENABLE | DCACHE_FLUSH, j2_ccr_base + cpu); 45 __raw_writel(CACHE_ENABLE | CACHE_FLUSH, j2_ccr_base + cpu);
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H A D | cache-sh4.c | 80 __raw_writel(0, icacheaddr + (j * PAGE_SIZE)); 148 __raw_writel(ccr, SH_CCR); 171 __raw_writel(0, addr); addr += entry_offset; 172 __raw_writel(0, addr); addr += entry_offset; 173 __raw_writel(0, addr); addr += entry_offset; 174 __raw_writel(0, addr); addr += entry_offset; 175 __raw_writel(0, addr); addr += entry_offset; 176 __raw_writel(0, addr); addr += entry_offset; 177 __raw_writel(0, addr); addr += entry_offset; 178 __raw_writel( [all...] |
/linux-master/arch/sh/include/asm/ |
H A D | watchdog.h | 80 __raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT); 92 __raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST); 113 __raw_writel((WTCSR_HIGH << 24) | (__u32)val, WTCSR);
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/linux-master/include/asm-generic/ |
H A D | logic_io.h | 59 #define __raw_writel __raw_writel macro 60 void __raw_writel(u32 value, volatile void __iomem *addr);
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/linux-master/arch/mips/pic32/pic32mzda/ |
H A D | early_console.c | 56 __raw_writel(0, uart_base + U_MODE(port)); 57 __raw_writel(((pbclk / baud) / 16) - 1, uart_base + U_BRG(port)); 58 __raw_writel(UART_ENABLE, uart_base + U_MODE(port)); 59 __raw_writel(UART_ENABLE_TX | UART_ENABLE_RX, 159 __raw_writel(c, uart_base + U_TXR(console_port));
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/linux-master/arch/arm/mach-s5pv210/ |
H A D | pm.c | 112 __raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK); 115 __raw_writel(__pa_symbol(s5pv210_cpu_resume), S5P_INFORM0); 119 __raw_writel(tmp, S5P_SLEEP_CFG); 125 __raw_writel(tmp, S5P_PWR_CFG); 130 __raw_writel(tmp, S5P_OTHERS);
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/linux-master/arch/arm/mach-pxa/ |
H A D | irq.c | 72 __raw_writel(icmr, base + ICMR); 82 __raw_writel(icmr, base + ICMR); 129 __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw)); 160 __raw_writel(0, base + ICMR); /* disable all IRQs */ 161 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ 164 __raw_writel(1, irq_base(0) + ICCR); 190 __raw_writel(0, base + ICMR); 208 __raw_writel(saved_icmr[i], base + ICMR); 209 __raw_writel(0, base + ICLR); 214 __raw_writel(saved_ip [all...] |
/linux-master/arch/arm/mach-davinci/ |
H A D | pm.c | 52 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); 59 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); 66 __raw_writel(val, pm_config.deepsleep_reg); 76 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); 81 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); 89 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); 98 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
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/linux-master/drivers/soc/ixp4xx/ |
H A D | ixp4xx-qmgr.c | 37 __raw_writel(val, &qmgr_regs->acc[queue][0]); 129 __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), 147 __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]); 172 __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]); 193 __raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */ 212 __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask, 224 __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask, 226 __raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */ 313 __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]); 363 __raw_writel( [all...] |
/linux-master/arch/sh/boards/ |
H A D | board-magicpanelr2.c | 67 __raw_writel(0x36db0400, CS2BCR); 69 __raw_writel(0x000003c0, CS2WCR); 73 __raw_writel(0x00000200, CS4BCR); 75 __raw_writel(0x00100981, CS4WCR); 79 __raw_writel(0x00000200, CS5ABCR); 81 __raw_writel(0x00100981, CS5AWCR); 85 __raw_writel(0x00000200, CS5BBCR); 87 __raw_writel(0x00100981, CS5BWCR); 91 __raw_writel(0x00000200, CS6ABCR); 93 __raw_writel( [all...] |
/linux-master/arch/arm/mach-s3c/ |
H A D | pm-gpio.c | 48 __raw_writel(gpcon, base + OFFS_CON); 52 __raw_writel(gps_gpdat, base + OFFS_DAT); 53 __raw_writel(gps_gpcon, base + OFFS_CON); 132 __raw_writel(chip->pm_save[2], base + OFFS_UP); 175 __raw_writel(gpcon, base + OFFS_CON); 179 __raw_writel(gps_gpdat, base + OFFS_DAT); 180 __raw_writel(gps_gpcon, base + OFFS_CON); 253 __raw_writel(gpcon, con); 276 __raw_writel(chip->pm_save[2], base + OFFS_DAT); 277 __raw_writel(chi [all...] |
/linux-master/arch/mips/kernel/ |
H A D | gpio_txx9.c | 32 __raw_writel(val, &txx9_pioptr->dout); 49 __raw_writel(__raw_readl(&txx9_pioptr->dir) & ~(1 << offset), 62 __raw_writel(__raw_readl(&txx9_pioptr->dir) | (1 << offset),
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/linux-master/arch/m68k/coldfire/ |
H A D | m54xx.c | 82 __raw_writel(0, MCF_GPT_GMS0); 83 __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0); 84 __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
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/linux-master/arch/mips/ath25/ |
H A D | early_printk.c | 21 __raw_writel(ch, base + 4 * reg);
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/linux-master/arch/mips/pic32/common/ |
H A D | reset.c | 32 __raw_writel(1, reg);
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/linux-master/arch/m68k/include/asm/ |
H A D | io_no.h | 25 #define __raw_writel(b, addr) (void)((*(__force volatile u32 *) (addr)) = (b)) macro 94 __raw_writel(value, addr); 96 __raw_writel(swab32(value), addr); 106 #define writel __raw_writel
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/linux-master/drivers/clocksource/ |
H A D | timer-ixp4xx.c | 88 __raw_writel(IXP4XX_OSST_TIMER_1_PEND, 105 __raw_writel((cycles & ~IXP4XX_OST_RELOAD_MASK) | val, 118 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET); 127 __raw_writel(IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT, 140 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET); 152 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET); 187 __raw_writel(0, tmr->base + IXP4XX_OSRT1_OFFSET); 190 __raw_writel(IXP4XX_OSST_TIMER_1_PEND, 194 __raw_writel(0, tmr->base + IXP4XX_OSTS_OFFSET);
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/linux-master/sound/soc/mxs/ |
H A D | mxs-saif.c | 154 __raw_writel(scr, master_saif->base + SAIF_CTRL); 196 __raw_writel(scr, master_saif->base + SAIF_CTRL); 221 __raw_writel(BM_SAIF_CTRL_CLKGATE, 223 __raw_writel(BM_SAIF_CTRL_RUN, 249 __raw_writel(BM_SAIF_CTRL_SFTRST, 253 __raw_writel(BM_SAIF_CTRL_CLKGATE, 278 __raw_writel(BM_SAIF_CTRL_RUN, 305 __raw_writel(BM_SAIF_CTRL_SFTRST, 307 __raw_writel(BM_SAIF_CTRL_CLKGATE, 367 __raw_writel(sc [all...] |
/linux-master/sound/soc/pxa/ |
H A D | mmp-sspa.c | 52 __raw_writel(sspa_sp, sspa->tx_base + SSPA_SP); 62 __raw_writel(sspa_sp, sspa->tx_base + SSPA_SP); 71 __raw_writel(sspa_sp, sspa->rx_base + SSPA_SP); 80 __raw_writel(sspa_sp, sspa->rx_base + SSPA_SP); 270 __raw_writel(sspa_ctrl, sspa->tx_base + SSPA_CTL); 271 __raw_writel(0x1, sspa->tx_base + SSPA_FIFO_UL); 273 __raw_writel(sspa_ctrl, sspa->rx_base + SSPA_CTL); 274 __raw_writel(0x0, sspa->rx_base + SSPA_FIFO_UL); 429 __raw_writel(sspa->sp, sspa->tx_base + SSPA_SP); 430 __raw_writel(ssp [all...] |
/linux-master/arch/mips/pci/ |
H A D | pci-ar71xx.c | 124 __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR); 138 __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR); 155 __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE); 156 __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA); 169 __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD); 170 __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), 216 __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA); 264 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); 281 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); 299 __raw_writel( [all...] |
/linux-master/drivers/soc/bcm/brcmstb/pm/ |
H A D | pm-mips.c | 81 __raw_writel(val, base + (idx << 2)) 140 __raw_writel(tmp, base + AON_CTRL_HOST_MISC_CMDS); 143 __raw_writel(0, base + AON_CTRL_PM_INITIATE); 145 __raw_writel(BSP_CLOCK_STOP | PM_INITIATE, 164 __raw_writel(0x10, base + AON_CTRL_PM_CPU_WAIT_COUNT); 168 __raw_writel(PM_COLD_CONFIG, base + AON_CTRL_PM_CTRL); 171 __raw_writel((PM_COLD_CONFIG | PM_PWR_DOWN), base + 196 __raw_writel(tmp, ctrl.aon_ctrl_base + AON_CTRL_RESET_CTRL); 206 __raw_writel(tmp, ctrl.memcs[i].ddr_phy_base + 209 __raw_writel(tm [all...] |
/linux-master/arch/sh/boards/mach-dreamcast/ |
H A D | rtc.c | 68 __raw_writel((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H); 69 __raw_writel((adj & 0xffff), AICA_RTC_SECS_L);
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/linux-master/arch/sh/include/mach-common/mach/ |
H A D | magicpanelr2.h | 21 #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg) 24 #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg)
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