Searched refs:x1 (Results 276 - 300 of 5674) sorted by relevance

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/linux-master/drivers/gpu/host1x/hw/
H A Dhw_host1x05_channel.h50 return (r >> 11) & 0x1;
92 return (r >> 0) & 0x1;
116 return (v & 0x1) << 2;
/linux-master/drivers/iio/dac/
H A Dad5624r.h13 #define AD5624R_ADDR_DAC1 0x1
19 #define AD5624R_CMD_UPDATE_DAC_N 0x1
28 #define AD5624R_LDAC_PWRDN_1K 0x1
/linux-master/scripts/dtc/include-prefixes/dt-bindings/dma/
H A Dat91.h25 #define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */
30 #define AT91_XDMAC_DT_MEM_IF_MASK (0x1)
37 #define AT91_XDMAC_DT_PER_IF_MASK (0x1)
/linux-master/include/dt-bindings/dma/
H A Dat91.h25 #define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */
30 #define AT91_XDMAC_DT_MEM_IF_MASK (0x1)
37 #define AT91_XDMAC_DT_PER_IF_MASK (0x1)
/linux-master/tools/testing/selftests/arm64/signal/
H A Dsignals.S14 /* fake_sigreturn x0:&sigframe, x1:sigframe_size, x2:misalign_bytes */
20 mov x21, x1
31 mov x1, x21
37 mov x1, x20
/linux-master/drivers/scsi/bnx2fc/
H A D57xx_hsi_bnx2fc.h23 #define B577XX_DOORBELL_HDR_RX (0x1<<0)
25 #define B577XX_DOORBELL_HDR_DB_TYPE (0x1<<1)
132 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
134 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1)
136 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2)
138 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3)
140 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4)
312 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
316 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
332 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<
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/linux-master/arch/x86/include/uapi/asm/
H A Ddebugreg.h21 #define DR_TRAP0 (0x1) /* db0 */
41 #define DR_RW_WRITE (0x1)
58 #define DR_LOCAL_ENABLE (0x1) /* Local enable for reg 0 */
/linux-master/drivers/target/
H A Dtarget_core_xcopy.h56 #define RCR_OP_MAX_SG_DESC_COUNT 0x1
59 #define RCR_OP_TOTAL_CONCURR_COPIES 0x1 /* Must be <= 16384 */
60 #define RCR_OP_MAX_CONCURR_COPIES 0x1 /* Must be <= 255 */
/linux-master/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpsoc_etr_masks.h29 #define PSOC_ETR_STS_FULL_MASK 0x1
59 #define PSOC_ETR_CTL_TRACECAPTEN_MASK 0x1
91 #define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1
117 #define PSOC_ETR_FFSR_FLINPROG_MASK 0x1
123 #define PSOC_ETR_FFCR_ENFT_MASK 0x1
149 #define PSOC_ETR_ITMISCOP0_ACQCOMP_MASK 0x1
155 #define PSOC_ETR_ITTRFLIN_TRIGIN_MASK 0x1
161 #define PSOC_ETR_ITATBDATA0_ATDATASBIT0_MASK 0x1
181 #define PSOC_ETR_ITATBCTR2_ATREADYS_MASK 0x1
193 #define PSOC_ETR_ITATBCTR0_ATVALIDS_MASK 0x1
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/linux-master/include/uapi/rdma/
H A Dmlx5_user_ioctl_verbs.h44 MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_TX = 0x1,
52 MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x1,
85 MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC = 0x1,
/linux-master/drivers/gpu/drm/xe/
H A Dxe_pcode_api.h17 #define PCODE_ILLEGAL_CMD 0x1
36 #define DGFX_INIT_STATUS_COMPLETE 0x1
48 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
/linux-master/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-375.c23 MPP_FUNCTION(0x1, "dev", "ad2"),
29 MPP_FUNCTION(0x1, "dev", "ad3"),
35 MPP_FUNCTION(0x1, "dev", "ad4"),
43 MPP_FUNCTION(0x1, "dev", "ad5"),
51 MPP_FUNCTION(0x1, "dev", "ad6"),
57 MPP_FUNCTION(0x1, "dev", "ad7"),
64 MPP_FUNCTION(0x1, "dev", "ad0"),
70 MPP_FUNCTION(0x1, "dev", "ad1"),
77 MPP_FUNCTION(0x1, "dev", "bootcs"),
94 MPP_FUNCTION(0x1, "de
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/linux-master/drivers/crypto/
H A Datmel-tdes-regs.h15 #define TDES_MR_TDESMOD_TDES (0x1 << 1)
21 #define TDES_MR_SMOD_AUTO (0x1 << 8)
25 #define TDES_MR_OPMOD_CBC (0x1 << 12)
28 #define TDES_MR_LOD (0x1 << 15)
31 #define TDES_MR_CFBS_32b (0x1 << 16)
51 #define TDES_ISR_URAT_ODR (0x1 << 12)
/linux-master/drivers/staging/fbtft/
H A Dfb_uc1611.c165 | (0x0 & 0x1) << 2 /* Increment positively */
166 | (0x1 << 1) /* Increment page first */
167 | 0x1); /* Wrap around (default) */
171 | (0x0 & 0x1) << 2 /* Mirror Y OFF */
172 | (0x0 & 0x1) << 1 /* Mirror X OFF */
173 | (0x0 & 0x1)); /* MS nibble last (default) */
178 | (0x0 & 0x1) << 2 /* Increment positively */
179 | (0x0 & 0x1) << 1 /* Increment column first */
180 | 0x1); /* Wrap around (default) */
184 | (0x1 <<
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/linux-master/sound/soc/rockchip/
H A Drockchip_pdm.h27 #define PDM_RX_MASK (0x1 << 2)
28 #define PDM_RX_START (0x1 << 2)
30 #define PDM_RX_CLR_MASK (0x1 << 0)
31 #define PDM_RX_CLR_WR (0x1 << 0)
70 #define PDM_CLK_640FS (0x1 << 0)
81 #define PDM_HPF_60HZ (0x1 << 0)
/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_6_ppsmc.h27 #define PPSMC_Result_OK 0x1
34 #define PPSMC_MSG_TestMessage 0x1
98 #define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1
103 #define PPSMC_THROTTLING_LIMIT_TYPE_SOCKET 0x1
107 #define PPSMC_AID_THM_TYPE 0x1
113 #define PPSMC_PLPD_MODE_DEFAULT 0x1
/linux-master/arch/arm/boot/dts/nxp/imx/
H A Dimx53-pinfunc.h14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
29 #define MX53_PAD_KEY_ROW0__GPIO4_7 0x028 0x350 0x000 0x1 0x0
31 #define MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x028 0x350 0x890 0x4 0x1
35 #define MX53_PAD_KEY_COL1__GPIO4_8 0x02c 0x354 0x000 0x1 0x0
42 #define MX53_PAD_KEY_ROW1__GPIO4_9 0x030 0x358 0x000 0x1 0x0
44 #define MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x030 0x358 0x898 0x4 0x1
49 #define MX53_PAD_KEY_COL2__GPIO4_10 0x034 0x35c 0x000 0x1 0x0
56 #define MX53_PAD_KEY_ROW2__GPIO4_11 0x038 0x360 0x000 0x1 0x0
63 #define MX53_PAD_KEY_COL3__GPIO4_12 0x03c 0x364 0x000 0x1
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/linux-master/scripts/dtc/include-prefixes/arm/nxp/imx/
H A Dimx53-pinfunc.h14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
29 #define MX53_PAD_KEY_ROW0__GPIO4_7 0x028 0x350 0x000 0x1 0x0
31 #define MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x028 0x350 0x890 0x4 0x1
35 #define MX53_PAD_KEY_COL1__GPIO4_8 0x02c 0x354 0x000 0x1 0x0
42 #define MX53_PAD_KEY_ROW1__GPIO4_9 0x030 0x358 0x000 0x1 0x0
44 #define MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x030 0x358 0x898 0x4 0x1
49 #define MX53_PAD_KEY_COL2__GPIO4_10 0x034 0x35c 0x000 0x1 0x0
56 #define MX53_PAD_KEY_ROW2__GPIO4_11 0x038 0x360 0x000 0x1 0x0
63 #define MX53_PAD_KEY_COL3__GPIO4_12 0x03c 0x364 0x000 0x1
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/df/
H A Ddf_1_7_sh_mask.h26 #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1
38 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
/linux-master/drivers/gpu/drm/exynos/
H A Dregs-decon7.h24 #define VIDOUTCON0_DISP_IF_0_ON (0x1 << 24)
27 #define VIDOUTCON0_IF_MASK (0x1 << 23)
29 #define VIDOUTCON0_I80IF (0x1 << 23)
59 #define WINCONx_TRIPLE_BUF_MODE (0x1 << 18)
62 #define WINCONx_BURSTLEN_8WORD (0x1 << 11)
63 #define WINCONx_BURSTLEN_MASK (0x1 << 11)
78 #define WINCONx_BPPMODE_32BPP_ABGR (0x1 << 2)
200 #define BLENDE_COEF_ONE 0x1
230 #define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
239 #define VIDINTCON0_FIFOLEVEL_TO25PC (0x1 <<
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/linux-master/include/sound/
H A Dtlv320aic32x4.h30 #define AIC32X4_MFP2_GPIO_OUT_HIGH 0x1
38 #define AIC32X4_MFP5_GPIO_OUT_HIGH 0x1
/linux-master/arch/arm/mach-omap2/
H A Dcm-regbits-24xx.h30 #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
50 #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
/linux-master/sound/soc/codecs/
H A Dmax98520.h70 #define MAX98520_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 2)
72 #define MAX98520_PCM_FORMAT_LJ (0x1 << 3)
77 #define MAX98520_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6)
82 #define MAX98520_PCM_MODE_CFG_PCM_BCLKEDGE (0x1 << 4)
91 #define MAX98520_PCM_SR_11025 (0x1)
110 #define MAX98520_PCM_RX_EN_MASK (0x1 << 0)
111 #define MAX98520_PCM_RX_BYP_EN_MASK (0x1 << 1)
121 #define MAX98520_SPK_SAFE_EN_MASK (0x1 << MAX98520_DSP_SPK_SAFE_EN_SHIFT)
/linux-master/drivers/net/ethernet/allwinner/
H A Dsun4i-emac.h69 #define EMAC_INT_CTL_TX0_ABRT_EN (0x1 << 2)
70 #define EMAC_INT_CTL_TX1_ABRT_EN (0x1 << 3)
73 #define EMAC_INT_STA_TX0_COMPLETE (0x1)
74 #define EMAC_INT_STA_TX1_COMPLETE (0x1 << 1)
76 #define EMAC_INT_STA_TX0_ABRT (0x1 << 2)
77 #define EMAC_INT_STA_TX1_ABRT (0x1 << 3)
79 #define EMAC_INT_STA_RX_COMPLETE (0x1 << 8)
105 #define EMAC_MAC_SUPP_100M (0x1 << 8)
/linux-master/arch/arm/mach-mvebu/
H A Dmvebu-soc-id.h17 #define MV78XX0_A0_REV 0x1
24 #define ARMADA_370_A1_REV 0x1

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