/linux-master/drivers/mmc/host/ |
H A D | tifm_sd.c | 126 val = readl(sock->addr + SOCK_MMCSD_DATA); 387 cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16) 388 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18); 389 cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16) 390 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10); 391 cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16) 392 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08); 393 cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16) 394 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00); 428 | readl(soc [all...] |
/linux-master/drivers/ptp/ |
H A D | ptp_dfl_tod.c | 107 nanosec = readl(base + TOD_NANOSEC); 108 seconds_lsb = readl(base + TOD_SECONDSL); 109 seconds_msb = readl(base + TOD_SECONDSH); 135 rate = readl(base + TOD_CLK_FREQ); 193 period = readl(base + TOD_PERIOD); 237 nanosec = readl(base + TOD_NANOSEC); 238 seconds_lsb = readl(base + TOD_SECONDSL); 239 seconds_msb = readl(base + TOD_SECONDSH);
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/linux-master/arch/arm/mach-berlin/ |
H A D | platsmp.c | 37 val = readl(cpu_ctrl + CPU_RESET_NON_SC); 111 val = readl(cpu_ctrl + CPU_RESET_NON_SC);
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/linux-master/arch/arm/mach-socfpga/ |
H A D | socfpga.c | 72 temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); 85 temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
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/linux-master/drivers/phy/marvell/ |
H A D | phy-mvebu-cp110-utmi.c | 121 reg = readl(PORT_REGS(port) + UTMI_PLL_CTRL_REG); 128 reg = readl(PORT_REGS(port) + UTMI_CAL_CTRL_REG); 134 reg = readl(PORT_REGS(port) + UTMI_TX_CH_CTRL_REG); 140 reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG); 149 reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG); 158 reg = readl(PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG); 218 reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG); 233 reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
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/linux-master/drivers/usb/host/ |
H A D | xhci-ext-caps.h | 133 val = readl(base + XHCI_HCC_PARAMS_OFFSET); 141 val = readl(base + offset);
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/linux-master/drivers/rtc/ |
H A D | rtc-mv.c | 73 rtc_time = readl(ioaddr + RTC_TIME_REG_OFFS); 74 rtc_date = readl(ioaddr + RTC_DATE_REG_OFFS); 104 rtc_time = readl(ioaddr + RTC_ALARM_TIME_REG_OFFS); 105 rtc_date = readl(ioaddr + RTC_ALARM_DATE_REG_OFFS); 125 alm->enabled = !!readl(ioaddr + RTC_ALARM_INTERRUPT_MASK_REG_OFFS); 191 if (!readl(ioaddr + RTC_ALARM_INTERRUPT_CASUE_REG_OFFS)) 228 rtc_time = readl(pdata->ioaddr + RTC_TIME_REG_OFFS); 238 rtc_time = readl(pdata->ioaddr + RTC_TIME_REG_OFFS);
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H A D | rtc-vt8500.c | 88 isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS); 106 date = readl(vt8500_rtc->regbase + VT8500_RTC_DR); 107 time = readl(vt8500_rtc->regbase + VT8500_RTC_TR); 144 alarm = readl(vt8500_rtc->regbase + VT8500_RTC_AS); 145 isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS); 175 unsigned long tmp = readl(vt8500_rtc->regbase + VT8500_RTC_AS);
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/linux-master/drivers/edac/ |
H A D | zynqmp_edac.c | 137 p->ceinfo.fault_lo = readl(base + CE_FFD0_OFST); 138 p->ceinfo.fault_hi = readl(base + CE_FFD1_OFST); 139 p->ceinfo.addr = (OCM_BASEVAL | readl(base + CE_FFA_OFST)); 143 p->ueinfo.fault_lo = readl(base + UE_FFD0_OFST); 144 p->ueinfo.fault_hi = readl(base + UE_FFD1_OFST); 145 p->ueinfo.addr = (OCM_BASEVAL | readl(base + UE_FFA_OFST)); 194 regval = readl(priv->baseaddr + OCM_ISR_OFST); 219 return readl(base + ECC_CTRL_OFST) & OCM_ECC_ENABLE_MASK;
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H A D | highbank_mc_edac.c | 61 status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS); 64 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR); 72 u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT); 74 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR); 92 reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT); 208 control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
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/linux-master/drivers/scsi/csiostor/ |
H A D | csio_defs.h | 56 return readl(addr) + ((u64)readl(addr + 4) << 32);
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/linux-master/drivers/video/fbdev/savage/ |
H A D | savagefb-i2c.c | 50 r = readl(chan->ioaddr + chan->reg); 56 readl(chan->ioaddr + chan->reg); /* flush posted write */ 64 r = readl(chan->ioaddr + chan->reg); 70 readl(chan->ioaddr + chan->reg); /* flush posted write */ 77 return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SCL_IN)); 84 return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SDA_IN));
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/linux-master/drivers/gpu/drm/sun4i/ |
H A D | sun4i_hdmi_tmds_clk.c | 131 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 135 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 154 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 160 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 173 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG); 186 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG);
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/linux-master/drivers/clk/keystone/ |
H A D | gate.c | 77 mdctl = readl(control_base + MDCTL); 85 pdstat = readl(domain_base + PDSTAT); 87 pdctl = readl(domain_base + PDCTL); 95 ptstat = readl(domain_transition_base + PTSTAT); 100 mdstat = readl(control_base + MDSTAT); 108 u32 mdstat = readl(data->control_base + MDSTAT);
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/linux-master/drivers/mailbox/ |
H A D | armada-37xx-rwtm-mailbox.c | 49 rx_msg.retval = readl(mbox->base + RWTM_MBOX_RETURN_STATUS); 51 rx_msg.status[i] = readl(mbox->base + RWTM_MBOX_STATUS(i)); 62 reg = readl(mbox->base + RWTM_HOST_INT_RESET); 87 reg = readl(mbox->base + RWTM_MBOX_FIFO_STATUS); 117 reg = readl(mbox->base + RWTM_HOST_INT_MASK); 130 reg = readl(mbox->base + RWTM_HOST_INT_MASK);
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/linux-master/drivers/clk/mvebu/ |
H A D | kirkwood.c | 88 u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) & 110 u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar)); 132 u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar)); 139 u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) & 157 u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK; 179 u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
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/linux-master/drivers/clk/socfpga/ |
H A D | clk-gate-s10.c | 30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; 43 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; 60 parent = ((readl(socfpgaclk->bypass_reg) & mask) >> 67 second_bypass = readl(socfpgaclk->bypass_reg - 90 parent = ((readl(socfpgaclk->bypass_reg) & mask) >> 97 second_bypass = readl(socfpgaclk->bypass_reg -
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/linux-master/drivers/clk/imx/ |
H A D | clk-gate-93.c | 52 val = readl(gate->reg + AUTHEN_OFFSET); 57 val = readl(gate->reg + DIRECT_OFFSET); 103 u32 val = readl(gate->reg + AUTHEN_OFFSET); 106 val = readl(gate->reg + LPM_CUR_OFFSET); 110 val = readl(gate->reg); 187 authen = readl(reg + AUTHEN_OFFSET);
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/linux-master/drivers/clocksource/ |
H A D | timer-npcm7xx.c | 61 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); 73 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); 85 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); 100 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); 115 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); 178 val = readl(timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
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H A D | timer-sun4i.c | 50 u32 old = readl(base + TIMER_CNTVAL_REG(1)); 52 while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS) 58 u32 val = readl(base + TIMER_CTL_REG(timer)); 72 u32 val = readl(base + TIMER_CTL_REG(timer)); 165 return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1)); 214 val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG);
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/linux-master/drivers/irqchip/ |
H A D | irq-csky-apb-intc.c | 153 readl(reg_base + GX_INTC_PEN63_32), 32); 158 readl(reg_base + GX_INTC_PEN31_00), 0); 207 ret = handle_irq_perbit(regs, readl(reg_pen_hi), 32); 211 ret = handle_irq_perbit(regs, readl(reg_pen_lo), 0); 220 readl(reg_pen_hi + CK_INTC_DUAL_BASE), 96); 225 readl(reg_pen_lo + CK_INTC_DUAL_BASE), 64);
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/linux-master/drivers/net/ethernet/stmicro/stmmac/ |
H A D | dwmac1000_dma.c | 21 u32 value = readl(ioaddr + DMA_AXI_BUS_MODE); 76 u32 value = readl(ioaddr + DMA_BUS_MODE); 156 u32 csr6 = readl(ioaddr + DMA_CONTROL); 185 u32 csr6 = readl(ioaddr + DMA_CONTROL); 223 readl(ioaddr + DMA_BUS_MODE + i * 4); 229 u32 hw_cap = readl(ioaddr + DMA_HW_FEATURE);
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/linux-master/drivers/clk/ |
H A D | clk-lan966x.c | 70 u32 val = readl(gck->reg); 81 u32 val = readl(gck->reg); 92 u32 div, val = readl(gck->reg); 110 u32 div, val = readl(gck->reg); 143 u32 val = readl(gck->reg); 151 u32 val = readl(gck->reg);
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/linux-master/drivers/watchdog/ |
H A D | sunxi_wdt.c | 91 val = readl(wdt_base + regs->wdt_cfg); 98 val = readl(wdt_base + regs->wdt_mode); 112 val = readl(wdt_base + regs->wdt_mode); 144 reg = readl(wdt_base + regs->wdt_mode); 180 reg = readl(wdt_base + regs->wdt_cfg); 187 reg = readl(wdt_base + regs->wdt_mode);
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/linux-master/drivers/i2c/busses/ |
H A D | i2c-axxia.c | 158 int_en = readl(idev->base + MST_INT_ENABLE); 166 int_en = readl(idev->base + MST_INT_ENABLE); 194 while (readl(idev->base + SOFT_RESET) & 1) { 275 size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO); 279 int c = readl(idev->base + MST_DATA); 307 size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO); 319 u32 fifo_status = readl(idev->base + SLV_RX_FIFO); 329 val = readl(idev->base + SLV_DATA); 333 readl(idev->base + SLV_DATA); /* dummy read */ 337 readl(ide [all...] |