Searched refs:registers (Results 251 - 275 of 278) sorted by relevance

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/linux-master/sound/soc/codecs/
H A Dwm5102.c27 #include <linux/mfd/arizona/registers.h>
H A Dcs47l92.c25 #include <linux/mfd/madera/registers.h>
H A Darizona.c20 #include <linux/mfd/arizona/registers.h>
H A Dcs47l85.c25 #include <linux/mfd/madera/registers.h>
H A Dcs47l90.c25 #include <linux/mfd/madera/registers.h>
H A Dwm5110.c27 #include <linux/mfd/arizona/registers.h>
H A Dmadera.c20 #include <linux/mfd/madera/registers.h>
979 /* use legacy frequency registers */
4257 /* FLL_AO_HOLD must be set before configuring any registers */
4317 * registers
4386 * as the FLL config registers are automatically applied when the FLL
4401 /* ctrl_up gates the writes to all the fll's registers, setting it to 0
4406 * registers
4510 /* Some sanity checks before any registers are written. */
4581 /* FLLn_HOLD must be set before configuring any registers */
H A Dwm8994.c31 #include <linux/mfd/wm8994/registers.h>
2261 * registers will actually be written but we avoid GCC flow
/linux-master/drivers/mfd/
H A Dcs47l92-tables.c16 #include <linux/mfd/madera/registers.h>
H A Dwm5102-tables.c14 #include <linux/mfd/arizona/registers.h>
H A Dcs47l85-tables.c13 #include <linux/mfd/madera/registers.h>
H A Dcs47l90-tables.c13 #include <linux/mfd/madera/registers.h>
H A Dwm5110-tables.c13 #include <linux/mfd/arizona/registers.h>
/linux-master/drivers/gpu/drm/msm/adreno/
H A Da5xx_gpu.c140 /* Turn off protected mode to write to special registers */
516 /* Turn off protected mode to write to special registers */
809 * config registers, which will make the "valid transaction" inside
836 /* Protect registers from the CP */
1471 * These are a list of the registers that need to be read through the HLSQ
1514 /* Count how many additional registers to get from the HLSQ aperture */
1622 /* Dump the additional a5xx HLSQ registers */
1626 drm_printf(p, "registers-hlsq:\n");
1635 * for each register type but not all of the registers
1636 * in the range are valid. Fortunately invalid registers
[all...]
H A Da6xx_gpu.c119 /* Turn off protected mode to write to special registers */
202 * GPU registers so we need to add 0x1a800 to the register value on A630
1067 /* Don't re-program the registers if they are already correct */
1071 /* Disable SP clock before programming HWCG registers */
1337 * Enable access protection to privileged registers, fault on an access
1347 /* Intentionally skip writing to some registers */
1913 /* Protect registers from the CP */
3044 adreno_gpu->registers = NULL;
/linux-master/drivers/net/ethernet/sfc/falcon/
H A Dfalcon.c1400 /* Restore the multicast hash registers. */
1905 * registers, so move into XGMII loopback if available */
1916 tests->registers =
/linux-master/drivers/usb/gadget/udc/
H A Dnet2272.c582 /* re-initialize endpoint transfer registers
1288 static DEVICE_ATTR_RO(registers);
2115 * read-only registers.
2156 * - NET2272 has two revision registers. The NET2270 legacy revision
2322 * BAR 0 holds PLX 9054 config registers
2324 * BAR 2 holds EPLD config registers
2325 * BAR 3 holds NET2272 registers
2407 * BAR 0 holds FGPA config registers
2408 * BAR 1 holds NET2272 registers
H A Dnet2280.c302 /* Make sure all the registers are written before ep_rsp*/
1799 static DEVICE_ATTR_RO(registers);
3653 /* BAR 0 holds all the registers
/linux-master/drivers/net/wireless/ath/ath10k/
H A Dsdio.c784 * flag that we should re-check IRQ status registers again
959 * registers and the lookahead registers.
969 /* Update only those registers that are enabled */
1060 /* An optimization to bypass reading the IRQ status registers
1064 * registers which can re-wake the target.
2286 crash_data->registers[i] = __cpu_to_le32(reg_dump_values[i]);
H A Dpci.c1466 crash_data->registers[i] = reg_dump_values[i];
3405 /* Arrange for access to Target SoC registers. */
/linux-master/arch/m68k/ifpsp060/src/
H A Dfpsp.S2406 # (3) The "fmovm.l" instruction w/ 2 or 3 control registers. #
2974 # the instruction is a fmovm.l with 2 or 3 registers.
8495 movm.l &0x3f00,-(%sp) # save some registers {d2-d7}
8519 movm.l (%sp)+,&0xfc # restore registers {d2-d7}
8541 movm.l (%sp)+,&0xfc # restore registers {d2-d7}
9792 movm.l &0x3f00,-(%sp) # save data registers
18081 # then the address registers have not been updated.
18182 # string of FP registers affected. This value is used as an index into #
18527 # easily changed if they were inputs passed in registers.
19200 # fmovm_ctrl(): emulate fmovm.l of control registers inst
[all...]
/linux-master/drivers/net/ethernet/sfc/
H A Def10.c2060 /* The hardware provides 'low' and 'high' (doorbell) registers
3455 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
/linux-master/drivers/gpu/drm/radeon/
H A Dradeon.h442 * Tiling registers
661 * GPU scratch registers structures, functions & helpers
2428 /* srbm instance registers */
2562 * Indirect registers accessors.
2815 const u32 *registers,
/linux-master/drivers/scsi/smartpqi/
H A Dsmartpqi_init.c3115 "timed out waiting for PQI all registers ready\n");
4386 * The offset registers are not initialized to the correct
8647 "failed to map memory for controller registers\n");
8666 ctrl_info->registers = ctrl_info->iomem_base;
8667 ctrl_info->pqi_registers = &ctrl_info->registers->pqi_registers;
/linux-master/arch/x86/crypto/
H A Daesni-intel_avx-x86_64.S262 # clobbering all xmm registers

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