Searched refs:regs (Results 26 - 50 of 167) sorted by relevance

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/haiku/src/system/libroot/posix/glibc/regex/
H A Dregex.c39 # define re_match_2(bufp, string1, size1, string2, size2, pos, regs, stop) \
40 __re_match_2 (bufp, string1, size1, string2, size2, pos, regs, stop)
41 # define re_match(bufp, string, size, pos, regs) \
42 __re_match (bufp, string, size, pos, regs)
43 # define re_search(bufp, string, size, startpos, range, regs) \
44 __re_search (bufp, string, size, startpos, range, regs)
48 # define re_search_2(bufp, st1, s1, st2, s2, startpos, range, regs, stop) \
49 __re_search_2 (bufp, st1, s1, st2, s2, startpos, range, regs, stop)
/haiku/src/add-ons/kernel/drivers/graphics/radeon/
H A Dmem_controller.c42 uint32 aper0 = INREG( di->regs, RADEON_CONFIG_APER_0_BASE );
119 tom = INREG( di->regs, RADEON_NB_TOM );
140 vuint8 *regs = di->regs; local
159 OUTREGP( regs, RADEON_AIC_CNTL, RADEON_PCIGART_TRANSLATE_EN,
163 OUTREG( regs, RADEON_AIC_PT_BASE, di->pci_gart.GATT.phys );
167 OUTREG( regs, RADEON_AIC_LO_ADDR, si->memory[mt_PCI].virtual_addr_start );
168 OUTREG( regs, RADEON_AIC_HI_ADDR, si->memory[mt_PCI].virtual_addr_start +
172 OUTREG( regs, RADEON_MC_AGP_LOCATION, 0xffffffc0 /* EK magic numbers from X.org
177 OUTREG( regs, RADEON_AGP_COMMAN
[all...]
H A Dirq.c21 OUTREG(di->regs, RADEON_GEN_INT_CNTL, 0);
30 Radeon_ThreadInterruptWork(vuint8 *regs, device_info *di, uint32 int_status) argument
71 Radeon_HandleCaptureInterrupt(vuint8 *regs, device_info *di, uint32 cap_status) argument
93 OUTREG(regs, RADEON_CAP_INT_STATUS, cap_status);
106 vuint8 *regs = di->regs; local
110 full_int_status = INREG(regs, RADEON_GEN_INT_STATUS);
111 int_status = full_int_status & INREG(regs, RADEON_GEN_INT_CNTL);
116 handled = Radeon_ThreadInterruptWork(regs, di, int_status);
119 OUTREG(regs, RADEON_GEN_INT_STATU
154 vuint8 *regs = di->regs; local
[all...]
H A Dinit.c40 int regs = 2; local
65 di->pcii.u.h0.base_registers[regs],
66 di->pcii.u.h0.base_registers[regs] + di->pcii.u.h0.base_register_sizes[regs] - 1 );
68 sprintf( buffer, "%04X_%04X_%02X%02X%02X regs",
74 di->pcii.u.h0.base_registers[regs],
75 di->pcii.u.h0.base_register_sizes[regs],
80 (void **)&(di->regs));
313 di->dac2_cntl = INREG( di->regs, RADEON_DAC_CNTL2 );
316 si->tmds_pll_cntl = INREG( di->regs, RADEON_TMDS_PLL_CNT
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/haiku/src/add-ons/accelerants/radeon/
H A Dinternal_tv_out.c93 vuint8 *regs = ai->regs; local
99 OUTREG( regs, mapping->address, *(uint32 *)((char *)(values) + mapping->offset) );
114 Radeon_OUTPLL( ai->regs, ai->si->asic,
129 vuint8 *regs = ai->regs;
135 OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_TV_HOST_RD_WT_CNTL_RD);
142 status = INREG( regs, RADEON_TV_HOST_RD_WT_CNTL );
148 OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, 0);
149 res = INREG( regs, RADEON_TV_HOST_READ_DAT
161 vuint8 *regs = ai->regs; local
233 vuint8 *regs = ai->regs; local
[all...]
H A Dcrtc.c22 vuint8 *regs = ai->regs; local
27 OUTREGP( regs, RADEON_CRTC_GEN_CNTL, values->crtc_gen_cntl,
30 OUTREG( regs, RADEON_CRTC_H_TOTAL_DISP, values->crtc_h_total_disp );
31 OUTREG( regs, RADEON_CRTC_H_SYNC_STRT_WID, values->crtc_h_sync_strt_wid );
32 OUTREG( regs, RADEON_CRTC_V_TOTAL_DISP, values->crtc_v_total_disp );
33 OUTREG( regs, RADEON_CRTC_V_SYNC_STRT_WID, values->crtc_v_sync_strt_wid );
34 OUTREG( regs, RADEON_CRTC_OFFSET_CNTL, values->crtc_offset_cntl );
35 OUTREG( regs, RADEON_CRTC_PITCH, values->crtc_pitch );
38 OUTREGP( regs, RADEON_CRTC2_GEN_CNT
[all...]
H A DAcceleration.c73 OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, (vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT
92 OUTREG(ai->regs, RADEON_DP_CNTL, ((xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0)
96 OUTREG( ai->regs, RADEON_SRC_Y_X, (list->src_top << 16 ) | list->src_left);
97 OUTREG( ai->regs, RADEON_DST_Y_X, (list->dest_top << 16 ) | list->dest_left);
100 OUTREG( ai->regs, RADEON_DST_HEIGHT_WIDTH, ((list->height + 1) << 16 ) | (list->width + 1));
166 OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, ((vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT)
171 OUTREG(ai->regs, RADEON_DP_BRUSH_FRGD_CLR, colorIndex);
172 OUTREG(ai->regs, RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM));
178 OUTREG(ai->regs, RADEON_DST_Y_X, (list->top << 16) | list->left);
179 OUTREG(ai->regs, RADEON_DST_WIDTH_HEIGH
[all...]
H A Doverlay.c56 vuint8 *regs = ai->regs; local
68 OUTREG( regs, RADEON_OV0_SCALE_CNTL, RADEON_SCALER_SOFT_RESET );
69 OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );
70 OUTREG( regs, RADEON_OV0_FILTER_CNTL, // use fixed filter coefficients
75 OUTREG( regs, RADEON_OV0_KEY_CNTL, RADEON_GRAPHIC_KEY_FN_EQ |
78 OUTREG( regs, RADEON_OV0_TEST, 0 );
79 // OUTREG( regs, RADEON_FCP_CNTL, RADEON_FCP_CNTL_GND ); // disable capture clock
80 // OUTREG( regs, RADEON_CAP0_TRIG_CNTL, 0 ); // disable capturing
81 OUTREG( regs, RADEON_OV0_REG_LOAD_CNT
162 vuint8 *regs = ai->regs; local
317 vuint8 *regs = ai->regs; local
534 vuint8 *regs = ai->regs; local
[all...]
H A Dmonitor_routing.c25 // read regs needed for display device routing
29 vuint8 *regs = ai->regs; local
31 values->dac_cntl = INREG( regs, RADEON_DAC_CNTL );
32 values->dac_cntl2 = INREG( regs, RADEON_DAC_CNTL2 );
33 values->crtc_ext_cntl = INREG( regs, RADEON_CRTC_EXT_CNTL );
34 values->crtc2_gen_cntl = INREG( regs, RADEON_CRTC2_GEN_CNTL );
35 values->disp_output_cntl = INREG( regs, RADEON_DISP_OUTPUT_CNTL );
36 values->pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL );
37 values->vclk_ecp_cntl = Radeon_INPLL( ai->regs, a
422 vuint8 *regs = ai->regs; local
[all...]
H A DCursor.c25 OUTREG( ai->regs, RADEON_CUR_CLR0, 0xffffff );
26 OUTREG( ai->regs, RADEON_CUR_CLR1, 0 );
28 OUTREG( ai->regs, RADEON_CUR2_CLR0, 0xffffff );
29 OUTREG( ai->regs, RADEON_CUR2_CLR1, 0 );
197 OUTREG( ai->regs, RADEON_CUR_HORZ_VERT_OFF, RADEON_CUR_LOCK
200 OUTREG( ai->regs, RADEON_CUR_HORZ_VERT_POSN, RADEON_CUR_LOCK
203 OUTREG( ai->regs, RADEON_CUR_OFFSET,
206 OUTREG( ai->regs, RADEON_CUR2_HORZ_VERT_OFF, RADEON_CUR2_LOCK
209 OUTREG( ai->regs, RADEON_CUR2_HORZ_VERT_POSN, RADEON_CUR2_LOCK
212 OUTREG( ai->regs, RADEON_CUR2_OFFSE
[all...]
H A Dpalette.c41 OUTREG( ai->regs, RADEON_DAC_CNTL2,
45 OUTREG( ai->regs, RADEON_PALETTE_INDEX, 0 );
48 OUTREG( ai->regs, RADEON_PALETTE_DATA, (i << 16) | (i << 8) | i );
104 OUTREG( ai->regs, RADEON_DAC_CNTL2,
108 OUTREG( ai->regs, RADEON_PALETTE_INDEX, first );
111 OUTREG( ai->regs, RADEON_PALETTE_DATA,
H A DSetDisplayMode.c86 vuint8 *regs = ai->regs; local
90 OUTREG( regs, common_regs[i].reg, common_regs[i].val );
93 OUTREGP( regs, RADEON_CRTC_GEN_CNTL,
100 OUTREG( regs, RADEON_CRTC_MORE_CNTL, 0 );
111 vuint8 *regs = ai->regs; local
263 OUTREG( regs, RADEON_SURFACE_CNTL, surface_cntl );
283 SHOW_FLOW( 0, "RADEON_DAC_CNTL %08X ", INREG( regs, RADEON_DAC_CNTL ));
284 SHOW_FLOW( 0, "RADEON_DAC_CNTL2 %08X ", INREG( regs, RADEON_DAC_CNTL
[all...]
/haiku/src/system/boot/platform/bios_ia32/
H A Dvideo.cpp277 struct bios_regs regs; local
278 regs.eax = 0x4f14;
279 regs.ebx = 0x0102;
280 regs.ecx = scaling;
281 call_bios(0x10, &regs);
371 struct bios_regs regs; local
372 regs.eax = 0x4f15;
373 regs.ebx = 0;
375 regs.ecx = 0;
376 regs
421 struct bios_regs regs; local
442 struct bios_regs regs; local
584 struct bios_regs regs; local
715 bios_regs regs; local
725 bios_regs regs; local
736 bios_regs regs; local
747 bios_regs regs; local
757 bios_regs regs; local
[all...]
H A Ddevices.cpp174 struct bios_regs regs; local
175 regs.eax = BIOS_BOOT_CD_GET_STATUS;
176 regs.edx = 0;
177 regs.esi = kDataSegmentScratch;
178 call_bios(0x13, &regs);
180 if ((regs.flags & CARRY_FLAG) != 0)
204 struct bios_regs regs; local
205 regs.eax = BIOS_IS_EXT_PRESENT;
206 regs.ebx = 0x55aa;
207 regs
225 struct bios_regs regs; local
244 struct bios_regs regs; local
272 struct bios_regs regs; local
655 struct bios_regs regs; local
684 struct bios_regs regs; local
783 struct bios_regs regs; local
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/haiku/src/add-ons/kernel/generic/bios/
H A Dbios.cpp267 bios_interrupt(bios_state* state, uint8 vector, bios_regs* regs) argument
287 M.x86.R_EAX = regs->eax;
288 M.x86.R_EBX = regs->ebx;
289 M.x86.R_ECX = regs->ecx;
290 M.x86.R_EDX = regs->edx;
291 M.x86.R_EDI = regs->edi;
292 M.x86.R_ESI = regs->esi;
293 M.x86.R_EBP = regs->ebp;
294 M.x86.R_EFLG = regs->eflags | X86_EFLAGS_INTERRUPT | X86_EFLAGS_RESERVED1;
297 M.x86.R_DS = regs
[all...]
/haiku/src/add-ons/accelerants/neomagic/engine/
H A Dnm_globals.h5 extern vuint32 *regs, *regs2;
H A Dnm_globals.c15 vuint32 *regs, *regs2; variable
/haiku/headers/private/kernel/arch/arm64/
H A Darch_thread_types.h21 uint64 regs[14]; // x19-x30, sp, tpidr_el0 member in struct:arch_thread
/haiku/src/system/boot/platform/riscv/
H A Dvirtio.cpp53 VirtioRegs* volatile regs = gVirtioDevList[i].regs; local
54 if (regs->signature != kVirtioSignature) continue;
55 if (regs->deviceId == deviceId) {
85 VirtioDevice::VirtioDevice(const VirtioResources& devRes): fRegs(devRes.regs)
218 VirtioRegs* volatile regs = (VirtioRegs* volatile)base; local
222 dprintf(" signature: 0x%" B_PRIx32 "\n", regs->signature);
223 dprintf(" version: %" B_PRIu32 "\n", regs->version);
224 dprintf(" device id: %" B_PRIu32 "\n", regs->deviceId);
230 gVirtioDevList[gVirtioDevListLen].regs
246 VirtioRegs* volatile regs = devRes->regs; local
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/haiku/src/bin/keymap/
H A DKeymap.cpp362 struct re_registers regs; local
364 if (re_search(&versionBuf, buffer, length, 0, length, &regs) >= 0) {
365 sscanf(buffer + regs.start[1], "%" B_SCNu32, &fKeys.version);
366 } else if (re_search(&capslockBuf, buffer, length, 0, length, &regs)
368 sscanf(buffer + regs.start[1], "0x%" B_SCNx32, &fKeys.caps_key);
369 } else if (re_search(&scrolllockBuf, buffer, length, 0, length, &regs)
371 sscanf(buffer + regs.start[1], "0x%" B_SCNx32, &fKeys.scroll_key);
372 } else if (re_search(&numlockBuf, buffer, length, 0, length, &regs)
374 sscanf(buffer + regs.start[1], "0x%" B_SCNx32, &fKeys.num_key);
375 } else if (re_search(&lshiftBuf, buffer, length, 0, length, &regs)
1049 _ComputeChars(const char* buffer, struct re_registers& regs, int i, int& offset) argument
1077 _ComputeTables(const char* buffer, struct re_registers& regs, uint32& table) argument
[all...]
H A DKeymap.h55 struct re_registers& regs, int i,
58 struct re_registers& regs, uint32& table);
/haiku/src/libs/gnu/
H A Dsched_getcpu.cpp56 if ((cpuInfo.regs.ecx & IA32_FEATURE_RDPID) != 0) {
64 if ((cpuInfo.regs.edx & IA32_FEATURE_AMD_EXT_RDTSCP)!= 0) {
/haiku/src/system/boot/platform/efi/arch/arm64/
H A Darch_acpi.cpp22 gUART = new(sUART) ArchUARTPL011(uart.regs.start,
40 uart.regs.start = spcr->base_address.address;
41 uart.regs.size = B_PAGE_SIZE;
50 uart.regs.start, uart.irq, uart.clock);
/haiku/src/add-ons/accelerants/intel_810/
H A Di810_regs.h55 // General error reporting regs.
111 #define INREG8(addr) (*((vuint8*)(gInfo.regs + (addr))))
112 #define INREG16(addr) (*((vuint16*)(gInfo.regs + (addr))))
113 #define INREG32(addr) (*((vuint32*)(gInfo.regs + (addr))))
115 #define OUTREG8(addr, val) (*((vuint8*)(gInfo.regs + (addr))) = (val))
116 #define OUTREG16(addr, val) (*((vuint16*)(gInfo.regs + (addr))) = (val))
117 #define OUTREG32(addr, val) (*((vuint32*)(gInfo.regs + (addr))) = (val))
/haiku/src/system/kernel/arch/arm/
H A Darch_debug_console.cpp110 sArchDebugUART = arch_get_uart_pl011(args->arch_args.uart.regs.start,
114 sArchDebugUART = arch_get_uart_8250_omap(args->arch_args.uart.regs.start,
118 sArchDebugUART = arch_get_uart_8250(args->arch_args.uart.regs.start,

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