Searched refs:registers (Results 26 - 50 of 278) sorted by relevance

1234567891011>>

/linux-master/drivers/gpu/drm/msm/
H A DMakefile166 cmd_headergen = mkdir -p $(obj)/generated && $(PYTHON3) $(src)/registers/gen_header.py \
167 $(headergen-opts) --rnn $(src)/registers --xml $< c-defines > $@
169 $(obj)/generated/%.xml.h: $(src)/registers/adreno/%.xml \
170 $(src)/registers/adreno/adreno_common.xml \
171 $(src)/registers/adreno/adreno_pm4.xml \
172 $(src)/registers/freedreno_copyright.xml \
173 $(src)/registers/gen_header.py \
174 $(src)/registers/rules-fd.xsd \
178 $(obj)/generated/%.xml.h: $(src)/registers/display/%.xml \
179 $(src)/registers/freedreno_copyrigh
[all...]
/linux-master/arch/arm/include/asm/
H A Dvfpmacros.h30 @ read all the working registers back into the VFP
49 cmp \tmp, #2 @ 32 x 64bit registers?
56 @ write all the working registers out of the VFP
74 cmp \tmp, #2 @ 32 x 64bit registers?
/linux-master/arch/hexagon/include/asm/
H A Dthread_info.h15 #include <asm/registers.h>
H A Dprocessor.h14 #include <asm/registers.h>
/linux-master/drivers/char/agp/
H A Dintel-gtt.c67 u8 __iomem *registers; member in struct:_intel_private
187 intel_private.registers = ioremap(reg_addr, KB(64));
188 if (!intel_private.registers)
192 intel_private.registers+I810_PGETBL_CTL);
196 if ((readl(intel_private.registers+I810_DRAM_CTL)
208 writel(0, intel_private.registers+I810_PGETBL_CTL);
366 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
439 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
441 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
444 pgetbl_ctl = readl(intel_private.registers
[all...]
H A Dsworks-agp.c24 /* Memory mapped registers */
39 volatile u8 __iomem *registers; member in struct:_serverworks_private
240 writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH);
242 while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) {
251 writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH);
253 while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) {
269 /* Get the memory mapped registers */
272 serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
273 if (!serverworks_private.registers) {
278 writeb(0xA, serverworks_private.registers
[all...]
H A Dati-agp.c51 volatile u8 __iomem *registers; member in struct:_ati_generic_private
178 writel(1, ati_generic_private.registers+ATI_GART_CACHE_CNTRL);
179 readl(ati_generic_private.registers+ATI_GART_CACHE_CNTRL); /* PCI Posting. */
199 iounmap((volatile u8 __iomem *)ati_generic_private.registers);
208 /* Get the memory mapped registers */
210 ati_generic_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096);
212 if (!ati_generic_private.registers)
226 writel(0x60000, ati_generic_private.registers+ATI_GART_FEATURE_ID);
227 readl(ati_generic_private.registers+ATI_GART_FEATURE_ID); /* PCI Posting.*/
234 writel(agp_bridge->gatt_bus_addr, ati_generic_private.registers
[all...]
/linux-master/arch/nios2/include/asm/
H A Dprocessor.h21 #include <asm/registers.h>
/linux-master/drivers/net/dsa/mv88e6xxx/
H A Ddevlink.c272 u16 *registers; local
275 registers = kmalloc_array(32, sizeof(u16), GFP_KERNEL);
276 if (!registers)
283 err = mv88e6xxx_g1_read(chip, i, &registers[i]);
286 err = mv88e6xxx_g2_read(chip, i, &registers[i]);
293 kfree(registers);
297 *data = (u8 *)registers;
310 /* The FID is scattered over multiple registers. */
515 * spreads the information across all three VTU data registers -
631 u16 *registers; local
[all...]
/linux-master/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.c36 struct a6xx_gpu_state_obj *registers; member in struct:a6xx_gpu_state
462 * temporary ioremap for the registers
566 int count = RANGE(dbgahb->registers, j);
568 dbgahb->registers[j] - (dbgahb->base >> 2);
704 /* Skip registers that are not present on older generation */
706 cluster->registers == a660_fe_cluster)
710 cluster->registers == a6xx_ps_cluster)
724 int count = RANGE(cluster->registers, j);
726 in += CRASHDUMP_READ(in, cluster->registers[j],
987 /* Read registers fro
1672 a6xx_show_registers(const u32 *registers, u32 *data, size_t count, struct drm_printer *p) argument
1695 a7xx_show_registers_indented(const u32 *registers, u32 *data, struct drm_printer *p, unsigned indent) argument
1719 a7xx_show_registers(const u32 *registers, u32 *data, struct drm_printer *p) argument
1809 a6xx_show_cluster_data(const u32 *registers, int size, u32 *data, struct drm_printer *p) argument
[all...]
H A Dadreno_gpu.c696 /* Some targets prefer to collect their own registers */
697 if (!adreno_gpu->registers)
700 /* Count the number of registers */
701 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2)
702 count += adreno_gpu->registers[i + 1] -
703 adreno_gpu->registers[i] + 1;
705 state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL);
706 if (state->registers) {
709 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
710 u32 start = adreno_gpu->registers[
[all...]
/linux-master/drivers/char/xillybus/
H A Dxillybus_core.c147 ep->registers + fpga_msg_ctrl_reg);
280 iowrite32(0x03, ep->registers + fpga_msg_ctrl_reg); /* Message ACK */
401 ep->registers + fpga_dma_bufaddr_lowaddr_reg);
403 ep->registers + fpga_dma_bufaddr_highaddr_reg);
411 ep->registers + fpga_dma_bufno_reg);
418 ep->registers + fpga_dma_bufno_reg);
644 endpoint->registers + fpga_buf_ctrl_reg);
803 channel->endpoint->registers +
888 channel->endpoint->registers +
894 channel->endpoint->registers
[all...]
/linux-master/drivers/usb/storage/
H A Dshuttle_usbat.c92 /* USBAT ATA registers */
105 /* USBAT User I/O Data registers */
116 /* USBAT User I/O Enable registers */
335 * Stores critical information in internal registers in preparation for the execution
380 * registers where the byte count should be read for transferring the data.
514 unsigned char *registers,
555 * Write to multiple registers
591 data[j<<1] = registers[j];
671 * Write to multiple registers:
672 * Allows us to write specific data to any registers
512 usbat_hp8200e_rw_block_test(struct us_data *us, unsigned char access, unsigned char *registers, unsigned char *data_out, unsigned short num_registers, unsigned char data_reg, unsigned char status_reg, unsigned char timeout, unsigned char qualifier, int direction, void *buf, unsigned short len, int use_sg, int minutes) argument
677 usbat_multiple_write(struct us_data *us, unsigned char *registers, unsigned char *data_out, unsigned short num_registers) argument
1054 unsigned char registers[3] = { local
1112 unsigned char registers[7] = { local
1203 unsigned char registers[7] = { local
1288 usbat_hp8200e_handle_read10(struct us_data *us, unsigned char *registers, unsigned char *data, struct scsi_cmnd *srb) argument
1556 unsigned char registers[32]; local
[all...]
/linux-master/drivers/thermal/ti-soc-thermal/
H A Domap5-thermal-data.c16 * need to describe the individual registers and bit fields.
281 .registers = &omap5430_mpu_temp_sensor_registers,
290 .registers = &omap5430_gpu_temp_sensor_registers,
297 .registers = &omap5430_core_temp_sensor_registers,
/linux-master/drivers/mfd/
H A Dmt6397-core.c21 #include <linux/mfd/mt6323/registers.h>
22 #include <linux/mfd/mt6331/registers.h>
23 #include <linux/mfd/mt6357/registers.h>
24 #include <linux/mfd/mt6358/registers.h>
25 #include <linux/mfd/mt6359/registers.h>
26 #include <linux/mfd/mt6397/registers.h>
/linux-master/arch/arm/mm/
H A Dl2c-l2x0-resume.S34 @ The prefetch and power control registers are revision dependent
/linux-master/arch/arm/vfp/
H A Dvfphw.S37 VFPFLDMIA r0, r1 @ reload the working registers while
56 VFPFSTMIA r0, r2 @ save the working registers
120 @ d16 - d31 registers
145 @ d16 - d31 registers
/linux-master/include/linux/mfd/da9063/
H A Dcore.h15 #include <linux/mfd/da9063/registers.h>
/linux-master/arch/arm/mach-lpc32xx/
H A Dsuspend.S37 @ Save a copy of the used registers in IRAM, r0 is corrupted
/linux-master/arch/microblaze/include/asm/
H A Dprocessor.h13 #include <asm/registers.h>
/linux-master/arch/um/kernel/
H A Dexec.c19 #include <registers.h>
/linux-master/drivers/firewire/
H A Dinit_ohci1394_dma.c37 void __iomem *registers; member in struct:ohci
42 writel(data, ohci->registers + offset);
47 return readl(ohci->registers + offset);
211 /* Accessing some registers without LPS enabled may cause lock up */
232 * init_ohci1394_controller - Map the registers of the controller and init DMA
233 * This maps the registers of the specified controller and initializes it
248 ohci.registers = (void __iomem *)fix_to_virt(FIX_OHCI1394_BASE);
/linux-master/arch/x86/um/
H A Dsyscalls_64.c13 #include <registers.h>
52 * The FS_BASE/GS_BASE registers are saved in the ptrace register set.
/linux-master/drivers/iio/adc/
H A Dat91_adc.c136 (st->registers->channel_base + (ch * 4))
173 * struct at91_adc_reg_desc - Various informations relative to registers
174 * @channel_base: Base offset for the channel data registers
175 * @drdy_mask: Mask of the DRDY field in the relevant registers
176 * (Interruptions registers mostly)
211 struct at91_adc_reg_desc registers; member in struct:at91_adc_caps
226 const struct at91_adc_reg_desc *registers; member in struct:at91_adc_state
375 u32 status = at91_adc_readl(st, st->registers->status_register);
392 at91_adc_writel(st, st->registers->trigger_register,
399 at91_adc_writel(st, st->registers
[all...]
/linux-master/drivers/scsi/aic7xxx/aicasm/
H A Daicasm_symbol.c464 * Sort the registers by address with a simple insertion sort.
468 symlist_t registers; local
485 SLIST_INIT(&registers);
500 symlist_add(&registers, cursym, SYMLIST_SORT);
537 SLIST_FOREACH(curnode, &registers, links) {
585 regnode = symlist_search(&registers, regname);
597 regnode = symlist_search(&registers, regname);
602 while (SLIST_FIRST(&registers) != NULL) {
608 curnode = SLIST_FIRST(&registers);
609 SLIST_REMOVE_HEAD(&registers, link
[all...]

Completed in 315 milliseconds

1234567891011>>