| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.h | 32 void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.h | 31 struct dc;
33 void dcn30_init_hw(struct dc *dc);
35 struct dc *dc,
39 struct dc *dc,
43 struct dc *dc,
47 struct dc *d
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.h | 32 struct dc;
34 void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
44 void dcn35_init_hw(struct dc *dc);
50 void dcn35_power_down_on_boot(struct dc *dc);
52 bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);
54 void dcn35_z10_restore(const struct dc *d
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/dce60/ |
| H A D | dce60_resource.h | 31 struct dc;
36 struct dc *dc);
40 struct dc *dc);
44 struct dc *dc);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce80/ |
| H A D | dce80_hwseq.c | 27 #include "dc.h"
45 void dce80_hw_sequencer_construct(struct dc *dc) argument
47 dce110_hw_sequencer_construct(dc);
49 dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
50 dc->hwss.pipe_control_lock = dce_pipe_control_lock;
51 dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
52 dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
|
| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| H A D | dce80_resource.h | 31 struct dc;
36 struct dc *dc);
40 struct dc *dc);
44 struct dc *dc);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn303/ |
| H A D | dcn303_init.c | 28 #include "dc.h"
32 void dcn303_hw_sequencer_construct(struct dc *dc) argument
34 dcn30_hw_sequencer_construct(dc);
36 dc->hwseq->funcs.dpp_pg_control = dcn303_dpp_pg_control;
37 dc->hwseq->funcs.hubp_pg_control = dcn303_hubp_pg_control;
38 dc->hwseq->funcs.dsc_pg_control = dcn303_dsc_pg_control;
39 dc->hwseq->funcs.enable_power_gating_plane = dcn303_enable_power_gating_plane;
|
| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| H A D | dce112_resource.h | 31 struct dc;
36 struct dc *dc);
39 struct dc *dc,
46 struct dc *dc,
51 struct dc *dc,
|
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.h | 32 void dcn201_init_hw(struct dc *dc);
35 void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
36 void dcn201_plane_atomic_disconnect(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
37 void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
40 struct dc *dc,
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.h | 35 void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
36 int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,
|
| /linux-master/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_resource.h | 28 void link_get_cur_res_map(const struct dc *dc, uint32_t *map);
29 void link_restore_res_map(const struct dc *dc, uint32_t *map);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.h | 34 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc);
36 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.h | 34 struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc);
36 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.h | 31 void dcn20_log_color_state(struct dc *dc,
38 struct dc *dc,
41 struct dc *dc,
43 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
44 void dcn20_update_mpcc(struct dc *dc, struc
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.h | 31 struct dc;
34 struct dc *dc,
37 bool dcn21_s0i3_golden_init_wa(struct dc *dc);
40 const struct dc *dc,
44 const struct dc *dc,
55 bool dcn21_is_abm_supported(struct dc *d
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.h | 30 void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.h | 29 void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer_private.h | 75 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
76 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
77 void (*init_pipes)(struct dc *dc, struct dc_state *context);
78 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
79 void (*update_plane_addr)(const struct dc *dc,
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.h | 31 struct dc;
44 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
46 void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
48 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
53 bool dcn32_set_input_transfer_func(struct dc *dc,
60 bool dcn32_set_output_transfer_func(struct dc *d
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | link_enc_cfg.h | 39 const struct dc *dc,
58 struct dc *dc,
78 struct dc *dc,
83 struct dc *dc,
88 struct dc *dc,
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.h | 34 void dcn35_update_bw_bounding_box_fpu(struct dc *dc,
37 int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,
42 void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_state_priv.h | 45 struct dc_stream_state *dc_state_create_phantom_stream(const struct dc *dc,
48 struct dc_plane_state *dc_state_create_phantom_plane(struct dc *dc,
53 void dc_state_release_phantom_stream(const struct dc *dc,
56 void dc_state_release_phantom_plane(const struct dc *dc,
61 enum dc_status dc_state_add_phantom_stream(struct dc *dc,
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.h | 32 struct dc;
34 void dcn10_hw_sequencer_construct(struct dc *dc);
38 struct dc *dc,
42 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
46 struct dc *dc);
48 struct dc *d
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| H A D | dcn31_hwseq.h | 31 struct dc;
33 void dcn31_init_hw(struct dc *dc);
46 void dcn31_z10_restore(const struct dc *dc);
47 void dcn31_z10_save_init(struct dc *dc);
50 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config);
52 struct dc *d
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.h | 31 void dcn20_populate_dml_writeback_from_context(struct dc *dc,
39 void dcn20_calculate_dlg_params(struct dc *dc,
44 int dcn20_populate_dml_pipes_from_context(struct dc *dc,
48 void dcn20_calculate_wm(struct dc *dc,
57 void dcn20_update_bounding_box(struct dc *dc,
[all...] |