Searched refs:_id (Results 26 - 50 of 377) sorted by relevance

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/linux-master/drivers/clk/mediatek/
H A Dclk-mt8192-vdec.c33 #define GATE_VDEC0(_id, _name, _parent, _shift) \
34 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
36 #define GATE_VDEC1(_id, _name, _parent, _shift) \
37 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
39 #define GATE_VDEC2(_id, _name, _parent, _shift) \
40 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt8195-vdo0.c31 #define GATE_VDO0_0(_id, _name, _parent, _shift) \
32 GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
34 #define GATE_VDO0_1(_id, _name, _parent, _shift) \
35 GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
37 #define GATE_VDO0_2(_id, _name, _parent, _shift) \
38 GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
40 #define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \
41 GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
H A Dclk-mt8188-vdo0.c34 #define GATE_VDO0_0(_id, _name, _parent, _shift) \
35 GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
37 #define GATE_VDO0_1(_id, _name, _parent, _shift) \
38 GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
40 #define GATE_VDO0_2(_id, _name, _parent, _shift) \
41 GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
43 #define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \
44 GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
H A Dclk-gate.h39 #define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \
41 .id = _id, \
50 #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \
51 GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
H A Dclk-mt8186-infra_ao.c38 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
39 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
42 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
43 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
45 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
46 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
49 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
50 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
52 #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \
53 GATE_MTK_FLAGS(_id, _nam
[all...]
H A Dclk-mt8183-vdec.c26 #define GATE_VDEC0_I(_id, _name, _parent, _shift) \
27 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
30 #define GATE_VDEC1_I(_id, _name, _parent, _shift) \
31 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
H A Dclk-mt6797-vdec.c27 #define GATE_VDEC0(_id, _name, _parent, _shift) \
28 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
30 #define GATE_VDEC1(_id, _name, _parent, _shift) \
31 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt6779-vdec.c28 #define GATE_VDEC0_I(_id, _name, _parent, _shift) \
29 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
31 #define GATE_VDEC1_I(_id, _name, _parent, _shift) \
32 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
H A Dclk-mt8365-mfg.c25 #define GATE_MFG0(_id, _name, _parent, _shift) \
26 GATE_MTK(_id, _name, _parent, &mfg0_cg_regs, _shift, \
29 #define GATE_MFG1(_id, _name, _parent, _shift) \
30 GATE_MTK(_id, _name, _parent, &mfg1_cg_regs, _shift, \
H A Dclk-mt8186-mdp.c25 #define GATE_MDP0(_id, _name, _parent, _shift) \
26 GATE_MTK(_id, _name, _parent, &mdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
28 #define GATE_MDP2(_id, _name, _parent, _shift) \
29 GATE_MTK(_id, _name, _parent, &mdp2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
H A Dclk-mt8365-vdec.c25 #define GATE_VDEC0(_id, _name, _parent, _shift) \
26 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
29 #define GATE_VDEC1(_id, _name, _parent, _shift) \
30 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
H A Dclk-mt2701-vdec.c27 #define GATE_VDEC0(_id, _name, _parent, _shift) \
28 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
30 #define GATE_VDEC1(_id, _name, _parent, _shift) \
31 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt2712-vdec.c27 #define GATE_VDEC0(_id, _name, _parent, _shift) \
28 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
30 #define GATE_VDEC1(_id, _name, _parent, _shift) \
31 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt6765-audio.c27 #define GATE_AUDIO0(_id, _name, _parent, _shift) \
28 GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
30 #define GATE_AUDIO1(_id, _name, _parent, _shift) \
31 GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
H A Dclk-mt8167-vdec.c30 #define GATE_VDEC0_I(_id, _name, _parent, _shift) \
31 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
33 #define GATE_VDEC1_I(_id, _name, _parent, _shift) \
34 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
H A Dclk-mt8192-aud.c33 #define GATE_AUD0(_id, _name, _parent, _shift) \
34 GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
36 #define GATE_AUD1(_id, _name, _parent, _shift) \
37 GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
39 #define GATE_AUD2(_id, _name, _parent, _shift) \
40 GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
H A Dclk-mt8192-mm.c32 #define GATE_MM0(_id, _name, _parent, _shift) \
33 GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
35 #define GATE_MM1(_id, _name, _parent, _shift) \
36 GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
38 #define GATE_MM2(_id, _name, _parent, _shift) \
39 GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
H A Dclk-mt8195-vpp0.c31 #define GATE_VPP0_0(_id, _name, _parent, _shift) \
32 GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
34 #define GATE_VPP0_1(_id, _name, _parent, _shift) \
35 GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
37 #define GATE_VPP0_2(_id, _name, _parent, _shift) \
38 GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
/linux-master/drivers/regulator/
H A Dmax77826-regulator.c118 #define MAX77826_LDO(_id, _type) \
119 [MAX77826_LDO ## _id] = { \
120 .id = MAX77826_LDO ## _id, \
121 .name = "LDO"#_id, \
122 .of_match = of_match_ptr("LDO"#_id), \
128 .enable_reg = MAX77826_REG_LDO_OPMD1 + (_id - 1) / 4, \
129 .enable_mask = BIT(((_id - 1) % 4) * 2 + 1), \
130 .vsel_reg = MAX77826_REG_LDO1_CFG + (_id - 1), \
135 #define MAX77826_BUCK(_idx, _id, _ops) \
136 [MAX77826_ ## _id]
[all...]
H A Dmpq7920.c26 #define MPQ7920BUCK(_name, _id, _ilim) \
27 [MPQ7920_BUCK ## _id] = { \
28 .id = MPQ7920_BUCK ## _id, \
39 .csel_reg = MPQ7920_BUCK ##_id## _REG_C, \
43 MPQ7920_BUCK ## _id), \
44 .vsel_reg = MPQ7920_BUCK ##_id## _REG_A, \
47 .active_discharge_reg = MPQ7920_BUCK ##_id## _REG_B, \
49 .soft_start_reg = MPQ7920_BUCK ##_id## _REG_C, \
54 #define MPQ7920LDO(_name, _id, _ops, _ilim, _ilim_sz, _creg, _cmask) \
55 [MPQ7920_LDO ## _id]
[all...]
H A Dsm5703-regulator.c37 #define SM5703USBLDO(_name, _id) \
38 [SM5703_USBLDO ## _id] = { \
43 .id = SM5703_USBLDO ## _id, \
48 .enable_mask = SM5703_REG_EN_USBLDO ##_id, \
86 #define SM5703LDO(_name, _id) \
87 [SM5703_LDO ## _id] = { \
92 .id = SM5703_LDO ## _id, \
96 .vsel_reg = SM5703_REG_LDO ##_id, \
98 .enable_reg = SM5703_REG_LDO ##_id, \
/linux-master/sound/soc/mediatek/mt8195/
H A Dmt8195-audsys-clk.c28 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
29 .id = _id, \
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \
39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
42 #define GATE_AUD0(_id, _name, _parent, _bit) \
43 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
45 #define GATE_AUD1(_id, _name, _parent, _bit) \
46 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
48 #define GATE_AUD3(_id, _name, _parent, _bit) \
49 GATE_AFE(_id, _nam
[all...]
/linux-master/sound/soc/mediatek/mt8188/
H A Dmt8188-audsys-clk.c28 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
29 .id = _id, \
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \
39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
42 #define GATE_AUD0(_id, _name, _parent, _bit) \
43 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
45 #define GATE_AUD1(_id, _name, _parent, _bit) \
46 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
48 #define GATE_AUD3(_id, _name, _parent, _bit) \
49 GATE_AFE(_id, _nam
[all...]
/linux-master/sound/soc/mediatek/mt8186/
H A Dmt8186-audsys-clk.c27 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
28 .id = _id, \
37 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \
38 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
41 #define GATE_AUD0(_id, _name, _parent, _bit) \
42 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
44 #define GATE_AUD1(_id, _name, _parent, _bit) \
45 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
47 #define GATE_AUD2(_id, _name, _parent, _bit) \
48 GATE_AFE(_id, _nam
[all...]
/linux-master/drivers/clk/x86/
H A Dclk-cgu.h117 #define LGM_PLL(_id, _name, _pdata, _flags, \
120 .id = _id, \
146 #define LGM_DDIV(_id, _name, _pname, _flags, _reg, \
150 .id = _id, \
203 #define LGM_MUX(_id, _name, _pdata, _f, _reg, \
206 .id = _id, \
219 #define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \
222 .id = _id, \
241 #define LGM_GATE(_id, _name, _pname, _f, _reg, \
244 .id = _id, \
[all...]

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