Searched refs:tile (Results 26 - 50 of 141) sorted by path

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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv10.c1049 nv10_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) argument
1059 nvkm_wr32(device, NV10_PGRAPH_TLIMIT(i), tile->limit);
1060 nvkm_wr32(device, NV10_PGRAPH_TSIZE(i), tile->pitch);
1061 nvkm_wr32(device, NV10_PGRAPH_TILE(i), tile->addr);
1192 .tile = nv10_gr_tile,
H A Dnv15.c30 .tile = nv10_gr_tile,
H A Dnv17.c30 .tile = nv10_gr_tile,
H A Dnv20.c149 nv20_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) argument
159 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
160 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
161 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
164 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
166 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
168 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);
171 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
173 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
312 /* interesting.. the below overwrites some of the tile setu
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H A Dnv25.c109 .tile = nv20_gr_tile,
H A Dnv2a.c100 .tile = nv20_gr_tile,
H A Dnv30.c171 .tile = nv20_gr_tile,
H A Dnv34.c108 .tile = nv20_gr_tile,
H A Dnv35.c108 .tile = nv20_gr_tile,
H A Dnv40.c173 nv40_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) argument
189 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
190 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
191 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
192 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
193 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
194 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
198 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
199 nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);
204 nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile
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H A Dnv44.c31 nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) argument
44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch);
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit);
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr);
56 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
57 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile
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H A Dpriv.h23 void (*tile)(struct nvkm_gr *, int region, struct nvkm_fb_tile *); member in struct:nvkm_gr_func
H A Dtu102.c65 data |= bank[gr->tile[i + j]] << (j * 4);
66 bank[gr->tile[i + j]]++;
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
H A Dnv31.c113 nv31_mpeg_tile(struct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile) argument
118 nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch);
119 nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit);
120 nvkm_wr32(device, 0x00b000 + (i * 0x10), tile->addr);
266 .tile = nv31_mpeg_tile,
H A Dnv44.c196 .tile = nv31_mpeg_tile,
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dbase.c35 nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) argument
37 fb->func->tile.fini(fb, region, tile);
42 u32 pitch, u32 flags, struct nvkm_fb_tile *tile)
44 fb->func->tile.init(fb, region, addr, size, pitch, flags, tile);
48 nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) argument
51 if (fb->func->tile.prog) {
52 fb->func->tile.prog(fb, region, tile);
41 nvkm_fb_tile_init(struct nvkm_fb *fb, int region, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) argument
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H A Dnv10.c31 u32 flags, struct nvkm_fb_tile *tile)
33 tile->addr = 0x80000000 | addr;
34 tile->limit = max(1u, addr + size) - 1;
35 tile->pitch = pitch;
39 nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) argument
41 tile->addr = 0;
42 tile->limit = 0;
43 tile->pitch = 0;
44 tile->zcomp = 0;
48 nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) argument
30 nv10_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) argument
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H A Dnv1a.c31 .tile.regions = 8,
32 .tile.init = nv10_fb_tile_init,
33 .tile.fini = nv10_fb_tile_fini,
34 .tile.prog = nv10_fb_tile_prog,
H A Dnv20.c31 u32 flags, struct nvkm_fb_tile *tile)
33 tile->addr = 0x00000001 | addr;
34 tile->limit = max(1u, addr + size) - 1;
35 tile->pitch = pitch;
37 fb->func->tile.comp(fb, i, size, flags, tile);
38 tile->addr |= 2;
44 struct nvkm_fb_tile *tile)
48 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) {
49 if (!(flags & 2)) tile
30 nv20_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) argument
43 nv20_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) argument
60 nv20_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) argument
70 nv20_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) argument
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H A Dnv25.c31 struct nvkm_fb_tile *tile)
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) {
36 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */
37 else tile->zcomp = 0x00200000; /* Z24S8 */
38 tile->zcomp |= tile->tag->offset;
40 tile->zcomp |= 0x01000000;
48 .tile.regions = 8,
49 .tile.init = nv20_fb_tile_init,
50 .tile
30 nv25_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) argument
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H A Dnv30.c31 u32 flags, struct nvkm_fb_tile *tile)
35 tile->addr = (0 << 4);
37 if (fb->func->tile.comp) /* z compression */
38 fb->func->tile.comp(fb, i, size, flags, tile);
39 tile->addr = (1 << 4);
42 tile->addr |= 0x00000001; /* enable */
43 tile->addr |= addr;
44 tile->limit = max(1u, addr + size) - 1;
45 tile
30 nv30_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) argument
49 nv30_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) argument
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H A Dnv35.c31 struct nvkm_fb_tile *tile)
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) {
36 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */
37 else tile->zcomp |= 0x08000000; /* Z24S8 */
38 tile->zcomp |= ((tile->tag->offset ) >> 6);
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13;
41 tile->zcomp |= 0x40000000;
50 .tile
30 nv35_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) argument
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H A Dnv36.c31 struct nvkm_fb_tile *tile)
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) {
36 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */
37 else tile->zcomp |= 0x20000000; /* Z24S8 */
38 tile->zcomp |= ((tile->tag->offset ) >> 6);
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14;
41 tile->zcomp |= 0x80000000;
50 .tile
30 nv36_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) argument
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H A Dnv40.c31 struct nvkm_fb_tile *tile)
36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) {
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */
38 tile->zcomp |= ((tile->tag->offset ) >> 8);
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13;
41 tile->zcomp |= 0x40000000;
56 .tile.regions = 8,
57 .tile
30 nv40_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) argument
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H A Dnv41.c30 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) argument
33 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit);
34 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch);
35 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr);
37 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp);
50 .tile.regions = 12,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv40_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
54 .tile
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Completed in 224 milliseconds

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