Searched refs:clk (Results 201 - 225 of 4090) sorted by relevance

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/linux-master/drivers/clk/
H A Dclk-hsdk-pll.c8 #include <linux/clk-provider.h>
97 int (*update_rate)(struct hsdk_pll_clk *clk, unsigned long rate,
121 static inline void hsdk_pll_write(struct hsdk_pll_clk *clk, u32 reg, u32 val) argument
123 iowrite32(val, clk->regs + reg);
126 static inline u32 hsdk_pll_read(struct hsdk_pll_clk *clk, u32 reg) argument
128 return ioread32(clk->regs + reg);
131 static inline void hsdk_pll_set_cfg(struct hsdk_pll_clk *clk, argument
137 val = hsdk_pll_read(clk, CGU_PLL_CTRL);
147 dev_dbg(clk->dev, "write configuration: %#x\n", val);
149 hsdk_pll_write(clk, CGU_PLL_CTR
152 hsdk_pll_is_locked(struct hsdk_pll_clk *clk) argument
157 hsdk_pll_is_err(struct hsdk_pll_clk *clk) argument
173 struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw); local
205 struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw); local
223 hsdk_pll_comm_update_rate(struct hsdk_pll_clk *clk, unsigned long rate, const struct hsdk_pll_cfg *cfg) argument
243 hsdk_pll_core_update_rate(struct hsdk_pll_clk *clk, unsigned long rate, const struct hsdk_pll_cfg *cfg) argument
281 struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw); local
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H A Dclk-gpio.c12 #include <linux/clk-provider.h>
53 struct clk_gpio *clk = to_clk_gpio(hw); local
55 gpiod_set_value(clk->gpiod, 1);
62 struct clk_gpio *clk = to_clk_gpio(hw); local
64 gpiod_set_value(clk->gpiod, 0);
69 struct clk_gpio *clk = to_clk_gpio(hw); local
71 return gpiod_get_value(clk->gpiod);
82 struct clk_gpio *clk = to_clk_gpio(hw); local
84 gpiod_set_value_cansleep(clk->gpiod, 1);
91 struct clk_gpio *clk local
98 struct clk_gpio *clk = to_clk_gpio(hw); local
119 struct clk_gpio *clk = to_clk_gpio(hw); local
126 struct clk_gpio *clk = to_clk_gpio(hw); local
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/linux-master/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7269.c26 static struct clk r_clk = {
34 static struct clk extal_clk = {
38 static unsigned long pll_recalc(struct clk *clk) argument
40 return clk->parent->rate * PLL_RATE;
47 static struct clk pll_clk = {
53 static unsigned long peripheral0_recalc(struct clk *clk) argument
55 return clk->parent->rate / 8;
62 static struct clk peripheral0_cl
68 peripheral1_recalc(struct clk *clk) argument
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/linux-master/drivers/cpufreq/
H A Dspear-cpufreq.c16 #include <linux/clk.h>
28 struct clk *clk; member in struct:__anon172
34 static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq)
36 struct clk *sys_pclk;
39 * In SPEAr1340, cpu clk's parent sys clk can take input from
50 * As sys clk can have multiple source with their own range
72 * access a source clock (clk) which might not be ancestor of cpu at present.
76 static int spear1340_set_cpu_rate(struct clk *sys_pcl
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/linux-master/drivers/usb/host/
H A Dehci-st.c12 #include <linux/clk.h>
33 struct clk *clks[USB_MAX_CLKS];
34 struct clk *clk48;
67 int clk, ret; local
85 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) {
86 ret = clk_prepare_enable(priv->clks[clk]);
104 while (--clk >
118 int clk; local
153 int err, irq, clk = 0; local
254 int clk; local
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H A Dohci-st.c12 #include <linux/clk.h>
31 struct clk *clks[USB_MAX_CLKS];
32 struct clk *clk48;
47 int clk, ret; local
65 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) {
66 ret = clk_prepare_enable(priv->clks[clk]);
84 while (--clk >
99 int clk; local
133 int err, irq, clk = 0; local
235 int clk; local
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H A Dohci-platform.c17 #include <linux/clk.h>
40 struct clk *clks[OHCI_MAX_CLKS];
48 int clk, ret; local
50 for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++) {
51 ret = clk_prepare_enable(priv->clks[clk]);
59 while (--clk >= 0)
60 clk_disable_unprepare(priv->clks[clk]);
69 int clk; local
96 int err, irq, clk = 0; local
246 int clk; local
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/linux-master/drivers/clk/qcom/
H A Dkrait-cc.c12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
16 #include "clk-krait.h"
57 * clk framework itself would have changed the parent for the new rate.
69 static int krait_notifier_register(struct device *dev, struct clk *clk, argument
75 ret = devm_clk_notifier_register(dev, clk, &mux->clk_nb);
92 struct clk_hw *clk; local
113 clk = ERR_PTR(-ENOMEM);
122 clk
159 struct clk_hw *clk; local
240 struct clk_hw *clk; local
353 struct clk *clk, **clks; local
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H A Dclk-regmap-divider.h9 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
H A Dclk-regmap-mux.h9 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
/linux-master/drivers/clk/tegra/
H A Dclk-tegra210-emc.c7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clk/tegra.h>
15 #include "clk.h"
37 struct clk *parents[8];
107 static struct clk *tegra210_clk_emc_find_parent(struct tegra210_clk_emc *emc,
127 struct clk *clk; local
190 clk = tegra210_clk_emc_find_parent(emc, index);
191 if (IS_ERR(clk)) {
271 struct clk *clk; local
295 tegra210_clk_emc_attach(struct clk *clk, struct tegra210_clk_emc_provider *provider) argument
364 tegra210_clk_emc_detach(struct clk *clk) argument
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/linux-master/drivers/clk/meson/
H A Dsclk-div.h10 #include <linux/clk-provider.h>
/linux-master/drivers/clk/davinci/
H A Dpll-da850.c9 #include <linux/clk-provider.h>
10 #include <linux/clk/davinci.h>
91 struct clk *clk; local
95 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base);
96 clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0");
98 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
99 clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc0");
100 clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc1");
101 clk_register_clkdev(clk, "pll0_sysclk
200 struct clk *clk; local
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/linux-master/drivers/media/dvb-frontends/
H A Dmn88443x.h19 struct clk *mclk;
/linux-master/include/sound/
H A Dsh_fsi.h11 #include <linux/clk.h>
/linux-master/arch/mips/lantiq/xway/
H A DMakefile2 obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o
/linux-master/drivers/media/tuners/
H A Dfc2580.h22 * @clk: Clock frequency (0 = internal clock).
27 u32 clk; member in struct:fc2580_platform_data
/linux-master/drivers/gpu/drm/sun4i/
H A Dsun4i_drv.h12 #include <linux/clk.h>
/linux-master/include/linux/clk/
H A Dzynq.h14 struct clk *clk_register_zynq_pll(const char *name, const char *parent,
/linux-master/drivers/iommu/
H A Dmsm_iommu.h10 #include <linux/clk.h>
41 * clk: The bus clock for this IOMMU hardware instance
53 struct clk *clk; member in struct:msm_iommu_dev
54 struct clk *pclk;
/linux-master/arch/mips/lantiq/
H A DMakefile5 obj-y := irq.o clk.o prom.o
/linux-master/sound/soc/tegra/
H A Dtegra_asoc_machine.h6 struct clk;
31 struct clk *clk_pll_a_out0;
32 struct clk *clk_pll_a;
33 struct clk *clk_cdev1;
/linux-master/sound/soc/sof/mediatek/mt8195/
H A DMakefile2 snd-sof-mt8195-objs := mt8195.o mt8195-clk.o mt8195-loader.o
/linux-master/sound/soc/sof/mediatek/mt8186/
H A DMakefile2 snd-sof-mt8186-objs := mt8186.o mt8186-clk.o mt8186-loader.o
/linux-master/drivers/clocksource/
H A Dtimer-armada-370-xp.c31 #include <linux/clk.h>
335 struct clk *clk = of_clk_get_by_name(np, "fixed"); local
338 if (IS_ERR(clk)) {
340 return PTR_ERR(clk);
343 ret = clk_prepare_enable(clk);
347 timer_clk = clk_get_rate(clk);
356 struct clk *clk; local
359 clk
394 struct clk *clk; local
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