/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | vega10_powertune.h | 61 uint8_t SviLoadLineEn; 62 uint8_t SviLoadLineVddC; 63 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 64 uint8_t TDC_MAWt; 65 uint8_t TdcWaterfallCtl; 66 uint8_t DTEAmbientTempBase;
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_mes_ctx.h | 61 uint8_t ring[PAGE_SIZE * 4]; 66 uint8_t gds_backup[64 * 1024]; 78 uint8_t ring[PAGE_SIZE * 4]; 80 uint8_t mec_hpd[GFX10_MEC_HPD_SIZE]; 92 uint8_t ring[PAGE_SIZE * 4]; 95 uint8_t sdma_meta_data[AMDGPU_CSA_SDMA_SIZE];
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/linux-master/drivers/scsi/aic7xxx/ |
H A D | aic7xxx.h | 389 uint8_t scsi_status; /* Standard SCSI status byte */ 398 uint8_t scsi_status; /* SCSI status to give to initiator */ 399 uint8_t target_phases; /* Bitmap of phases to execute */ 400 uint8_t data_phase; /* Data-In or Data-Out */ 401 uint8_t initiator_tag; /* Initiator's transaction tag */ 412 uint8_t cdb[12]; 462 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 463 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 464 /*26*/ uint8_t lun; 465 /*27*/ uint8_t ta [all...] |
H A D | aic79xx.h | 398 uint8_t scsi_status; /* Standard SCSI status byte */ 404 uint8_t scsi_status; /* SCSI status to give to initiator */ 405 uint8_t target_phases; /* Bitmap of phases to execute */ 406 uint8_t data_phase; /* Data-In or Data-Out */ 407 uint8_t initiator_tag; /* Initiator's transaction tag */ 423 uint8_t cdblen; 425 uint8_t cdb[MAX_CDB_LEN]; 427 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 437 uint8_t scsi_status; /* SCSI status to give to initiator */ 438 uint8_t target_phase [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/bios/dce112/ |
H A D | command_table_helper_dce112.c | 34 static uint8_t phy_id_to_atom(enum transmitter t) 36 uint8_t atom_phy_id; 67 static uint8_t signal_type_to_atom_dig_mode(enum signal_type s) 69 uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP; 94 static uint8_t clock_source_id_to_atom_phy_clk_src_id( 97 uint8_t atom_phy_clk_src_id = 0; 120 static uint8_t hpd_sel_to_atom(enum hpd_source_id id) 122 uint8_t atom_hpd_sel = 0; 151 static uint8_t dig_encoder_sel_to_atom(enum engine_id id) 257 static uint8_t encoder_action_to_ato [all...] |
H A D | command_table_helper2_dce112.c | 34 static uint8_t phy_id_to_atom(enum transmitter t) 36 uint8_t atom_phy_id; 67 static uint8_t signal_type_to_atom_dig_mode(enum signal_type s) 69 uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP; 94 static uint8_t clock_source_id_to_atom_phy_clk_src_id( 97 uint8_t atom_phy_clk_src_id = 0; 120 static uint8_t hpd_sel_to_atom(enum hpd_source_id id) 122 uint8_t atom_hpd_sel = 0; 151 static uint8_t dig_encoder_sel_to_atom(enum engine_id id) 257 static uint8_t encoder_action_to_ato [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
H A D | dcn31_smu.h | 57 uint8_t WmSetting; 58 uint8_t WmType; // Used for normal pstate change or memory retraining 59 uint8_t Padding[2]; 90 uint8_t ActiveHystLimit; 91 uint8_t IdleHystLimit; 92 uint8_t FPS; 93 uint8_t MinActiveFreqType; 124 uint8_t WckRatio; 125 uint8_t Spare[3]; 140 uint8_t NumDcfClkLevelsEnable [all...] |
/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
H A D | smu13_driver_if_v13_0_4.h | 56 uint8_t WmSetting; 57 uint8_t WmType; // Used for normal pstate change or memory retraining 58 uint8_t Padding[2]; 89 uint8_t ActiveHystLimit; 90 uint8_t IdleHystLimit; 91 uint8_t FPS; 92 uint8_t MinActiveFreqType; 116 uint8_t WckRatio; 117 uint8_t Spare[3]; 132 uint8_t NumDcfClkLevelsEnable [all...] |
H A D | smu13_driver_if_yellow_carp.h | 55 uint8_t WmSetting; 56 uint8_t WmType; // Used for normal pstate change or memory retraining 57 uint8_t Padding[2]; 88 uint8_t ActiveHystLimit; 89 uint8_t IdleHystLimit; 90 uint8_t FPS; 91 uint8_t MinActiveFreqType; 115 uint8_t WckRatio; 116 uint8_t Spare[3]; 131 uint8_t NumDcfClkLevelsEnable [all...] |
H A D | smu12_driver_if.h | 56 uint8_t WmSetting; 57 uint8_t WmType; // Used for normal pstate change or memory retraining 58 uint8_t Padding[2]; 89 uint8_t ActiveHystLimit; 90 uint8_t IdleHystLimit; 91 uint8_t FPS; 92 uint8_t MinActiveFreqType; 124 uint8_t NumDcfClkDpmEnabled; 125 uint8_t NumSocClkDpmEnabled; 126 uint8_t NumFClkDpmEnable [all...] |
H A D | smu11_driver_if_vangogh.h | 55 uint8_t WmSetting; 56 uint8_t WmType; // Used for normal pstate change or memory retraining 57 uint8_t Padding[2]; 88 uint8_t ActiveHystLimit; 89 uint8_t IdleHystLimit; 90 uint8_t FPS; 91 uint8_t MinActiveFreqType; 143 uint8_t NumDfPstatesEnabled; 144 uint8_t NumDcfclkLevelsEnabled; 145 uint8_t NumDispClkLevelsEnable [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
H A D | dcn301_smu.h | 61 uint8_t WmSetting; 62 uint8_t WmType; // Used for normal pstate change or memory retraining 63 uint8_t Padding[2]; 114 uint8_t NumDfPstatesEnabled; 115 uint8_t NumDcfclkLevelsEnabled; 116 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk 117 uint8_t NumSocClkLevelsEnabled; 119 uint8_t IspClkLevelsEnabled; //applies to both ispiclk and ispxclk 120 uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk 121 uint8_t spar [all...] |
/linux-master/lib/raid6/ |
H A D | recov_neon_inner.c | 28 void __raid6_2data_recov_neon(int bytes, uint8_t *p, uint8_t *q, uint8_t *dp, 29 uint8_t *dq, const uint8_t *pbmul, 30 const uint8_t *qmul) 40 * uint8_t px, qx, db; 78 void __raid6_datap_recov_neon(int bytes, uint8_t *p, uint8_t *q, uint8_t *d [all...] |
H A D | mktables.c | 21 static uint8_t gfmul(uint8_t a, uint8_t b) 23 uint8_t v = 0; 35 static uint8_t gfpow(uint8_t a, int b) 37 uint8_t v = 1; 56 uint8_t v; 57 uint8_t exptbl[256], invtbl[256];
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/linux-master/include/xen/interface/io/ |
H A D | displif.h | 152 * Values: <uint8_t> 422 * operation - uint8_t, operation code, XENDISPL_OP_??? 834 * type - uint8_t, type of the event 862 uint8_t operation; 863 uint8_t reserved[5]; 872 uint8_t reserved[56]; 878 uint8_t operation; 879 uint8_t reserved; 883 uint8_t reserved1[56]; 889 uint8_t typ [all...] |
H A D | pvcalls.h | 20 uint8_t pad1[52]; 24 uint8_t pad2[52]; 51 uint8_t addr[28]; 59 uint8_t reuse; 63 uint8_t addr[28]; 82 uint8_t dummy[56]; 115 uint8_t dummy[8];
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/linux-master/drivers/gpu/drm/amd/display/include/ |
H A D | grph_object_ctrl_defs.h | 99 uint8_t hpd_int_gpio_uid; 100 uint8_t hpd_active; 175 uint8_t min_allowed_bl_level; 176 uint8_t remote_display_config; 182 uint8_t oem_i2c_obj_id; 242 uint8_t lane0:2; /* Mapping for lane 0 */ 243 uint8_t lane1:2; /* Mapping for lane 1 */ 244 uint8_t lane2:2; /* Mapping for lane 2 */ 245 uint8_t lane3:2; /* Mapping for lane 3 */ 247 uint8_t ra [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/bios/dce80/ |
H A D | command_table_helper_dce80.c | 36 static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action) 38 uint8_t atom_action = 0; 152 static uint8_t clock_source_id_to_atom_phy_clk_src_id( 155 uint8_t atom_phy_clk_src_id = 0; 178 static uint8_t signal_type_to_atom_dig_mode(enum signal_type s) 180 uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP; 208 static uint8_t hpd_sel_to_atom(enum hpd_source_id id) 210 uint8_t atom_hpd_sel = 0; 239 static uint8_t dig_encoder_sel_to_atom(enum engine_id id) 241 uint8_t atom_dig_encoder_se [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/bios/dce60/ |
H A D | command_table_helper_dce60.c | 36 static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action) 38 uint8_t atom_action = 0; 152 static uint8_t clock_source_id_to_atom_phy_clk_src_id( 155 uint8_t atom_phy_clk_src_id = 0; 178 static uint8_t signal_type_to_atom_dig_mode(enum signal_type s) 180 uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP; 208 static uint8_t hpd_sel_to_atom(enum hpd_source_id id) 210 uint8_t atom_hpd_sel = 0; 239 static uint8_t dig_encoder_sel_to_atom(enum engine_id id) 241 uint8_t atom_dig_encoder_se [all...] |
/linux-master/drivers/scsi/qla2xxx/ |
H A D | qla_nx2.h | 248 uint8_t shl; 249 uint8_t shr; 250 uint8_t index_a; 251 uint8_t rsvd; 273 uint8_t *buff; 274 uint8_t *stop_offset; 275 uint8_t *start_offset; 276 uint8_t *init_offset; 278 uint8_t seq_end; 279 uint8_t template_en [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/bios/dce110/ |
H A D | command_table_helper_dce110.c | 34 static uint8_t phy_id_to_atom(enum transmitter t) 36 uint8_t atom_phy_id; 67 static uint8_t signal_type_to_atom_dig_mode(enum signal_type s) 69 uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP; 97 static uint8_t clock_source_id_to_atom_phy_clk_src_id( 100 uint8_t atom_phy_clk_src_id = 0; 123 static uint8_t hpd_sel_to_atom(enum hpd_source_id id) 125 uint8_t atom_hpd_sel = 0; 154 static uint8_t dig_encoder_sel_to_atom(enum engine_id id) 255 static uint8_t encoder_action_to_ato [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/ |
H A D | dm_services_types.h | 124 uint8_t transmitter; 125 uint8_t ddi_channel_mapping; 126 uint8_t pipe_idx; 203 uint8_t display_count; 208 uint8_t crtc_index; 215 uint8_t luminance; 219 uint8_t signal_level; 227 uint8_t error_code; /* Byte 4 */ 228 uint8_t ac_level_percentage; /* Byte 5 */ 229 uint8_t dc_level_percentag [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
H A D | dcn35_smu.h | 54 uint8_t WmSetting; 55 uint8_t WmType; // Used for normal pstate change or memory retraining 56 uint8_t Padding[2]; 97 uint8_t WckRatio; 98 uint8_t Spare[3]; 116 uint8_t NumDcfClkLevelsEnabled; 117 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk 118 uint8_t NumSocClkLevelsEnabled; 119 uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk 120 uint8_t VpeClkLevelsEnable [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | aux_engine.h | 47 uint8_t *data; 102 uint8_t *buffer; 110 uint8_t returned_byte; 125 uint8_t *buffer; 132 uint8_t returned_byte; 141 uint8_t reply_data[DEFAULT_AUX_MAX_DATA_SIZE]; 168 uint8_t *buffer, 169 uint8_t *reply_result, 173 uint8_t *returned_bytes);
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/linux-master/drivers/gpu/drm/amd/display/dc/link/protocols/ |
H A D | link_dp_training_fixed_vs_pe_retimer.c | 48 const uint8_t vendor_lttpr_write_data_vs[3] = {0x0, 0x53, 0x63}; 49 const uint8_t vendor_lttpr_write_data_pe[3] = {0x0, 0x54, 0x63}; 50 uint8_t dprx_vs = 0; 51 uint8_t dprx_pe = 0; 52 uint8_t lane; 75 uint8_t lane_count) 77 const uint8_t vendor_lttpr_write_data_reset[4] = {0x1, 0x50, 0x63, 0xFF}; 78 uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0}; 79 uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0}; 80 uint8_t lan [all...] |