Searched refs:hwirq (Results 176 - 200 of 375) sorted by relevance

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/linux-master/drivers/pinctrl/
H A Dpinctrl-apple-gpio.c256 unsigned int irqgrp = FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq));
258 writel(BIT(data->hwirq % 32), pctl->base + REG_IRQ(irqgrp, data->hwirq));
284 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
286 gpiochip_disable_irq(gc, data->hwirq);
295 gpiochip_enable_irq(gc, data->hwirq);
296 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
305 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP,
308 apple_gpio_direction_input(chip, data->hwirq);
322 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MOD
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H A Dpinctrl-pistachio.c1224 gpio_mask_writel(bank, GPIO_INTERRUPT_STATUS, data->hwirq, 0);
1231 gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0);
1240 gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1);
1247 pistachio_gpio_direction_input(chip, data->hwirq);
1259 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
1260 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1262 gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1266 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
1267 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1269 gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
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/linux-master/drivers/pci/controller/
H A Dpcie-xilinx-cpm.c155 mask = BIT(data->hwirq + XILINX_CPM_PCIE_IDRN_SHIFT);
169 mask = BIT(data->hwirq + XILINX_CPM_PCIE_IDRN_SHIFT);
186 * @hwirq: HW interrupt number
191 unsigned int irq, irq_hw_number_t hwirq)
231 val &= ~BIT(d->hwirq);
243 val |= BIT(d->hwirq);
255 unsigned int irq, irq_hw_number_t hwirq)
337 switch (d->hwirq) {
345 if (intr_cause[d->hwirq].str)
346 dev_warn(dev, "%s\n", intr_cause[d->hwirq]
190 xilinx_cpm_pcie_intx_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) argument
254 xilinx_cpm_pcie_event_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) argument
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H A Dpcie-microchip-host.c446 u32 bitpos = data->hwirq;
458 msg->data = data->hwirq;
461 (int)data->hwirq, msg->address_hi, msg->address_lo);
510 if (test_bit(d->hwirq, msi->used))
511 __clear_bit(d->hwirq, msi->used);
513 dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq);
595 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
606 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
622 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
640 irq_hw_number_t hwirq)
639 mc_pcie_intx_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) argument
837 mc_pcie_event_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) argument
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/linux-master/arch/powerpc/platforms/pseries/
H A Dmsi.c541 irq_hw_number_t hwirq)
548 parent_fwspec.param[0] = hwirq;
565 int hwirq; local
568 hwirq = rtas_query_irq_number(pci_get_pdn(pdev), desc->msi_index);
569 if (hwirq < 0) {
570 dev_err(&pdev->dev, "Failed to query HW IRQ: %d\n", hwirq);
571 return hwirq;
575 phb->dn, virq, hwirq, nr_irqs);
578 ret = pseries_irq_parent_domain_alloc(domain, virq + i, hwirq + i);
582 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq
540 pseries_irq_parent_domain_alloc(struct irq_domain *domain, unsigned int virq, irq_hw_number_t hwirq) argument
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/linux-master/drivers/gpio/
H A Dgpio-mt7621.c110 int pin = d->hwirq;
114 gpiochip_enable_irq(gc, d->hwirq);
133 int pin = d->hwirq;
148 gpiochip_disable_irq(gc, d->hwirq);
156 int pin = d->hwirq;
H A Dgpio-virtio.c236 struct vgpio_irq_line *irq_line = &vgpio->irq_lines[d->hwirq];
251 struct vgpio_irq_line *irq_line = &vgpio->irq_lines[d->hwirq];
266 struct vgpio_irq_line *irq_line = &vgpio->irq_lines[d->hwirq];
277 struct vgpio_irq_line *irq_line = &vgpio->irq_lines[d->hwirq];
283 virtio_gpio_irq_prepare(vgpio, d->hwirq);
291 struct vgpio_irq_line *irq_line = &vgpio->irq_lines[d->hwirq];
332 struct vgpio_irq_line *irq_line = &vgpio->irq_lines[d->hwirq];
338 virtio_gpio_req(vgpio, VIRTIO_GPIO_MSG_IRQ_TYPE, d->hwirq, type,
345 virtio_gpio_irq_prepare(vgpio, d->hwirq);
H A Dgpio-bcm-kona.c334 unsigned gpio = d->hwirq;
355 unsigned gpio = d->hwirq;
377 unsigned gpio = d->hwirq;
399 unsigned gpio = d->hwirq;
461 int hwirq = GPIO_PER_BANK * bank_id + bit; local
470 hwirq);
481 return gpiochip_reqres_irq(&kona_gpio->gpio_chip, d->hwirq);
488 gpiochip_relres_irq(&kona_gpio->gpio_chip, d->hwirq);
514 irq_hw_number_t hwirq)
513 bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) argument
H A Dgpio-tegra.c274 unsigned int gpio = d->hwirq;
283 unsigned int gpio = d->hwirq;
293 unsigned int gpio = d->hwirq;
301 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
309 bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
371 unsigned int gpio = d->hwirq;
423 WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin);
432 unsigned int hwirq,
437 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
538 unsigned int gpio = d->hwirq;
431 tegra_gpio_child_to_parent_hwirq(struct gpio_chip *chip, unsigned int hwirq, unsigned int type, unsigned int *parent_hwirq, unsigned int *parent_type) argument
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H A Dgpio-xgs-iproc.c48 int pin = d->hwirq;
67 int pin = d->hwirq;
94 int pin = d->hwirq;
121 int pin = d->hwirq;
/linux-master/drivers/pinctrl/intel/
H A Dpinctrl-cherryview.c1176 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
1181 intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
1187 static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask) argument
1194 intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
1209 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
1211 chv_gpio_irq_mask_unmask(gc, hwirq, true);
1212 gpiochip_disable_irq(gc, hwirq);
1218 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
1220 gpiochip_enable_irq(gc, hwirq);
1221 chv_gpio_irq_mask_unmask(gc, hwirq, fals
1249 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
1332 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
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H A Dpinctrl-lynxpoint.c570 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
571 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT);
575 iowrite32(BIT(hwirq % 32), reg);
590 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
591 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
593 gpiochip_enable_irq(gc, hwirq);
596 iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
603 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
604 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
607 iowrite32(ioread32(reg) & ~BIT(hwirq
616 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
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/linux-master/drivers/irqchip/
H A Dirq-gic.c220 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
222 if (hwirq < 16)
223 hwirq = this_cpu_read(sgi_intid);
225 writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_EOI);
230 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
236 if (hwirq < 16)
237 hwirq = this_cpu_read(sgi_intid);
239 writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
827 writel_relaxed(2 << 24 | d->hwirq,
845 writel_relaxed(map << 16 | d->hwirq, gic_data_dist_bas
1081 gic_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
1140 irq_hw_number_t hwirq; local
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H A Dirq-imx-mu-msi.c100 imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(msi_data, data->hwirq));
107 imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, IMX_MU_xCR_RIEn(msi_data, data->hwirq), 0);
114 imx_mu_read(msi_data, msi_data->cfg->xRR + data->hwirq * 4);
135 u64 addr = msi_data->msiir_addr + 4 * data->hwirq;
139 msg->data = data->hwirq;
193 __clear_bit(d->hwirq, &msi_data->used);
H A Dirq-realtek-rtl.c59 value |= BIT(i->hwirq);
73 value &= ~BIT(i->hwirq);
H A Dirq-aspeed-i2c-ic.c51 unsigned int irq, irq_hw_number_t hwirq)
50 aspeed_i2c_ic_map_irq_domain(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) argument
H A Dirq-jcore-aic.c47 irq_hw_number_t hwirq)
46 jcore_aic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) argument
/linux-master/drivers/pinctrl/samsung/
H A Dpinctrl-s3c64xx.c307 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
333 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
358 shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
366 s3c64xx_irq_set_function(d, bank, irqd->hwirq);
517 val |= 1 << ddata->eints[irqd->hwirq];
519 val &= ~(1 << ddata->eints[irqd->hwirq]);
539 writel(1 << ddata->eints[irqd->hwirq],
564 shift = ddata->eints[irqd->hwirq];
576 s3c64xx_irq_set_function(d, bank, irqd->hwirq);
/linux-master/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c309 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
325 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
343 irq_hw_number_t hwirq)
371 phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
375 msg->data = data->hwirq;
378 (int)data->hwirq, msg->address_hi, msg->address_lo);
429 if (!test_bit(d->hwirq, msi->msi_irq_in_use))
431 d->hwirq);
433 __clear_bit(d->hwirq, msi->msi_irq_in_use);
342 mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) argument
/linux-master/drivers/memory/
H A Domap-gpmc.c1315 static int gpmc_irq_endis(unsigned long hwirq, bool endis) argument
1320 if (hwirq >= GPMC_NR_NAND_IRQS)
1321 hwirq += 8 - GPMC_NR_NAND_IRQS;
1325 regval |= BIT(hwirq);
1327 regval &= ~BIT(hwirq);
1335 gpmc_irq_endis(p->hwirq, false);
1340 gpmc_irq_endis(p->hwirq, true);
1345 gpmc_irq_endis(d->hwirq, false);
1350 gpmc_irq_endis(d->hwirq, true);
1353 static void gpmc_irq_edge_config(unsigned long hwirq, boo argument
1375 unsigned int hwirq = d->hwirq; local
1427 int hwirq, virq; local
1501 int hwirq; local
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/linux-master/drivers/ssb/
H A Ddriver_gpio.c146 int gpio, hwirq, err; local
165 hwirq = ssb_mips_irq(bus->chipco.dev) + 2;
166 err = request_irq(hwirq, ssb_gpio_irq_chipco_handler, IRQF_SHARED,
345 int gpio, hwirq, err; local
364 hwirq = ssb_mips_irq(bus->extif.dev) + 2;
365 err = request_irq(hwirq, ssb_gpio_irq_extif_handler, IRQF_SHARED,
/linux-master/drivers/mfd/
H A Dioc3.c50 unsigned int hwirq = irqd_to_hwirq(d); local
52 writel(BIT(hwirq), &ipd->regs->sio_ir);
58 unsigned int hwirq = irqd_to_hwirq(d); local
60 writel(BIT(hwirq), &ipd->regs->sio_iec);
66 unsigned int hwirq = irqd_to_hwirq(d); local
68 writel(BIT(hwirq), &ipd->regs->sio_ies);
79 irq_hw_number_t hwirq)
82 if (BIT(hwirq) & IOC3_LVL_MASK)
78 ioc3_irq_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) argument
/linux-master/drivers/platform/x86/intel/
H A Dcrystal_cove_charger.c69 charger->new_mask &= ~BIT(data->hwirq);
76 charger->new_mask |= BIT(data->hwirq);
/linux-master/arch/mips/ralink/
H A Dirq.c71 rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE);
76 rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE);
/linux-master/arch/xtensa/kernel/
H A Dirq.c35 asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs) argument
49 generic_handle_domain_irq(NULL, hwirq);

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