/linux-master/drivers/pci/controller/mobiveil/ |
H A D | pcie-mobiveil-host.c | 48 unsigned int devfn, int where) 59 return pcie->csr_axi_slave_base + where; 73 return rp->config_axi_slave_base + where; 47 mobiveil_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) argument
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/linux-master/drivers/pci/controller/ |
H A D | pci-aardvark.c | 1141 int where, int size, u32 *val) 1153 return pci_bridge_emul_conf_read(&pcie->bridge, where, 1161 allow_crs = (where == PCI_VENDOR_ID) && (size == 4) && 1178 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); 1205 *val = (*val >> (8 * (where & 3))) & 0xff; 1207 *val = (*val >> (8 * (where & 3))) & 0xffff; 1227 int where, int size, u32 val) 1240 return pci_bridge_emul_conf_write(&pcie->bridge, where, 1243 if (where % size) 1259 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 1140 advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) argument 1226 advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) argument [all...] |
H A D | pci-host-generic.c | 43 unsigned int devfn, int where) 48 return pci_ecam_map_bus(bus, devfn, where); 42 pci_dw_ecam_map_bus(struct pci_bus *bus, unsigned int devfn, int where) argument
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H A D | pci-hyperv.c | 1104 * @where: Offset within config space 1108 static void _hv_pcifront_read_config(struct hv_pci_dev *hpdev, int where, argument 1113 int offset = where + CFG_PAGE_OFFSET; 1119 if (where + size <= PCI_COMMAND) { 1120 memcpy(val, ((u8 *)&hpdev->desc.v_id) + where, size); 1121 } else if (where >= PCI_CLASS_REVISION && where + size <= 1123 memcpy(val, ((u8 *)&hpdev->desc.rev) + where - 1125 } else if (where >= PCI_SUBSYSTEM_VENDOR_ID && where 1226 _hv_pcifront_write_config(struct hv_pci_dev *hpdev, int where, int size, u32 val) argument 1288 hv_pcifront_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) argument 1316 hv_pcifront_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) argument [all...] |
H A D | pci-ixp4xx.c | 186 static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where) argument 191 return (PCI_CONF1_ADDRESS(0, 0, PCI_FUNC(devfn), where) & 196 PCI_FUNC(devfn), where) & 217 static int ixp4xx_crp_read_config(struct ixp4xx_pci *p, int where, int size, argument 222 n = where % 4; 223 cmd = where & ~3; 226 __func__, where, size, cmd); 255 static int ixp4xx_crp_write_config(struct ixp4xx_pci *p, int where, int size, argument 260 n = where % 4; 264 cmd |= where 293 ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) argument 340 ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) argument [all...] |
H A D | pci-loongson.c | 178 unsigned int devfn, int where) 187 addroff |= (devfn << 8) | where; 192 unsigned int devfn, int where) 201 addroff |= (devfn << 8) | (where & 0xff) | ((where & 0xf00) << 16); 213 unsigned int devfn, int where) 235 if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base) 236 return cfg0_map(priv, bus, devfn, where); 239 if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base) 240 return cfg1_map(priv, bus, devfn, where); 177 cfg0_map(struct loongson_pci *priv, struct pci_bus *bus, unsigned int devfn, int where) argument 191 cfg1_map(struct loongson_pci *priv, struct pci_bus *bus, unsigned int devfn, int where) argument 212 pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn, int where) argument [all...] |
H A D | pci-mvebu.c | 53 #define PCIE_CONF_ADDR(bus, devfn, where) \ 55 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ 348 static int mvebu_pcie_child_rd_conf(struct pci_bus *bus, u32 devfn, int where, argument 364 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), 369 *val = readb_relaxed(conf_data + (where & 3)); 372 *val = readw_relaxed(conf_data + (where & 2)); 385 int where, int size, u32 val) 400 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), 405 writeb(val, conf_data + (where & 3)); 408 writew(val, conf_data + (where 384 mvebu_pcie_child_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) argument 985 mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) argument 999 mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) argument [all...] |
H A D | pci-rcar-gen2.c | 106 int where) 120 if (slot == 0x0 && where >= 0x40) 127 return priv->reg + (slot >> 1) * 0x100 + where; 105 rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn, int where) argument
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H A D | pci-tegra.c | 419 unsigned int where) 421 return ((where & 0xf00) << 16) | (bus << 16) | (PCI_SLOT(devfn) << 11) | 422 (PCI_FUNC(devfn) << 8) | (where & 0xff); 427 int where) 438 addr = port->base + (where & ~3); 446 offset = tegra_pcie_conf_offset(bus->number, devfn, where); 460 int where, int size, u32 *value) 463 return pci_generic_config_read32(bus, devfn, where, size, 466 return pci_generic_config_read(bus, devfn, where, size, value); 470 int where, in 418 tegra_pcie_conf_offset(u8 bus, unsigned int devfn, unsigned int where) argument 425 tegra_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) argument 459 tegra_pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) argument 469 tegra_pcie_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) argument [all...] |
H A D | pci-thunder-ecam.c | 16 static void set_val(u32 v, int where, int size, u32 *val) argument 18 int shift = (where & 3) * 8; 20 pr_debug("set_val %04x: %08x\n", (unsigned int)(where & ~3), v); 30 unsigned int devfn, int where, int size, u32 *val) 36 int where_a = where & 0xc; 39 set_val(e0, where, size, val); 50 set_val(v, where, size, val); 68 set_val(v, where, size, val); 77 set_val(v, where, size, val); 84 int where, in 29 handle_ea_bar(u32 e0, int bar, struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) argument 83 thunder_ecam_p2_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) argument 122 thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) argument 319 thunder_ecam_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) argument [all...] |
H A D | pci-thunder-pem.c | 38 int where, int size, u32 *val) 44 if (devfn != 0 || where >= 2048) 52 read_val = where & ~3ull; 61 switch (where & ~3) { 68 * Change PME interrupt to vector 2 on T88 where it 122 read_val >>= (8 * (where & 3)); 138 int where, int size, u32 *val) 151 return thunder_pem_bridge_read(bus, devfn, where, size, val); 153 return pci_generic_config_read(bus, devfn, where, size, val); 214 int where, in 37 thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) argument 137 thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) argument 213 thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) argument 286 thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) argument [all...] |
H A D | pci-xgene.c | 163 int where, int size, u32 *val) 168 ret = pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val); 183 ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL)) 187 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); 162 xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) argument
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H A D | pcie-altera.c | 102 int (*rp_read_cfg)(struct altera_pcie *pcie, int where, 105 int where, int size, u32 value); 321 int where, u8 byte_en, bool read, u32 *headers) 335 headers[2] = TLP_CFG_DW2(bus, devfn, where); 339 int where, u8 byte_en, u32 *value) 343 get_tlp_header(pcie, bus, devfn, where, byte_en, true, 352 int where, u8 byte_en, u32 value) 357 get_tlp_header(pcie, bus, devfn, where, byte_en, false, 361 if ((where & 0x7) == 0) 376 if ((bus == pcie->root_bus_nr) && (where 320 get_tlp_header(struct altera_pcie *pcie, u8 bus, u32 devfn, int where, u8 byte_en, bool read, u32 *headers) argument 338 tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn, int where, u8 byte_en, u32 *value) argument 351 tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn, int where, u8 byte_en, u32 value) argument 382 s10_rp_read_cfg(struct altera_pcie *pcie, int where, int size, u32 *value) argument 402 s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno, int where, int size, u32 value) argument 429 _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno, unsigned int devfn, int where, int size, u32 *value) argument 473 _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno, unsigned int devfn, int where, int size, u32 value) argument 504 altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) argument 519 altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) argument [all...] |
H A D | pcie-brcmstb.c | 692 unsigned int devfn, int where) 700 return devfn ? NULL : base + PCIE_ECAM_REG(where); 709 return base + PCIE_EXT_CFG_DATA + PCIE_ECAM_REG(where); 713 unsigned int devfn, int where) 721 return devfn ? NULL : base + PCIE_ECAM_REG(where); 728 idx = PCIE_ECAM_OFFSET(bus->number, devfn, where); 691 brcm_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) argument 712 brcm7425_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) argument
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H A D | pcie-iproc.c | 243 * window where the MSI posted writes are written, for the writes to be 250 * To hold the address of the register where the MSI writes are 462 int where) 468 val = ALIGN_DOWN(PCIE_ECAM_OFFSET(busno, devfn, where), 4) | 508 * This will handle the case where CFG_RETRY_STATUS is 525 static void iproc_pcie_fix_cap(struct iproc_pcie *pcie, int where, u32 *val) argument 529 switch (where & ~0x3) { 569 int where, int size, u32 *val) 579 ret = pci_generic_config_read32(bus, devfn, where, size, val); 581 iproc_pcie_fix_cap(pcie, where, va 459 iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie, unsigned int busno, unsigned int devfn, int where) argument 568 iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) argument 623 iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie, int busno, unsigned int devfn, int where) argument 646 iproc_pcie_bus_map_cfg_bus(struct pci_bus *bus, unsigned int devfn, int where) argument 654 iproc_pci_raw_config_read32(struct iproc_pcie *pcie, unsigned int devfn, int where, int size, u32 *val) argument 672 iproc_pci_raw_config_write32(struct iproc_pcie *pcie, unsigned int devfn, int where, int size, u32 val) argument 696 iproc_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) argument 712 iproc_pcie_config_write32(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) argument [all...] |
H A D | pcie-mediatek-gen3.c | 191 * @where: offset in config space 197 int where, int size) 203 bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3); 212 int where) 216 return pcie->base + PCIE_CFG_OFFSET_ADDR + where; 220 int where, int size, u32 *val) 222 mtk_pcie_config_tlp_header(bus, devfn, where, size); 224 return pci_generic_config_read32(bus, devfn, where, size, val); 228 int where, int size, u32 val) 230 mtk_pcie_config_tlp_header(bus, devfn, where, siz 196 mtk_pcie_config_tlp_header(struct pci_bus *bus, unsigned int devfn, int where, int size) argument 211 mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) argument 219 mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) argument 227 mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) argument [all...] |
H A D | pcie-mediatek.c | 126 #define CFG_HEADER_DW1(where, size) \ 127 (GENMASK(((size) - 1), 0) << ((where) & 0x3)) 285 int where, int size, u32 *val) 292 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 293 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus), 309 *val = (*val >> (8 * (where & 3))) & 0xff; 311 *val = (*val >> (8 * (where & 3))) & 0xffff; 317 int where, int size, u32 val) 322 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 323 writel(CFG_HEADER_DW2(where, PCI_FUN 284 mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, int where, int size, u32 *val) argument 316 mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, int where, int size, u32 val) argument 363 mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) argument 376 mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) argument 759 mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) argument [all...] |
H A D | pcie-mt7621.c | 127 unsigned int devfn, int where) 131 PCI_FUNC(devfn), where); 135 return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3); 126 mt7621_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) argument
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H A D | pcie-rcar-host.c | 95 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) argument 97 unsigned int shift = BITS_PER_BYTE * (where & 3); 98 u32 val = rcar_pci_read_reg(pcie, where & ~3); 154 unsigned int devfn, int where, u32 *data) 169 reg = where & ~3; 233 int where, int size, u32 *val) 239 bus, devfn, where, val); 244 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff; 246 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff; 248 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where 152 rcar_pcie_config_access(struct rcar_pcie_host *host, unsigned char access_type, struct pci_bus *bus, unsigned int devfn, int where, u32 *data) argument 232 rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) argument 255 rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) argument [all...] |
H A D | pcie-rcar.c | 24 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) argument 26 unsigned int shift = BITS_PER_BYTE * (where & 3); 27 u32 val = rcar_pci_read_reg(pcie, where & ~3); 31 rcar_pci_write_reg(pcie, val, where & ~3);
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H A D | pcie-rcar.h | 139 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data);
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H A D | pcie-rockchip-host.c | 101 int where, int size, u32 *val) 105 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where; 126 int where, int size, u32 val) 131 offset = where & ~0x3; 139 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); 147 tmp |= val << ((where & 0x3) * 8); 155 int where, int size, u32 *val) 159 addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 188 int where, int size, u32 val) 192 addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 100 rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip, int where, int size, u32 *val) argument 125 rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip, int where, int size, u32 val) argument 153 rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) argument 186 rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip, struct pci_bus *bus, u32 devfn, int where, int size, u32 val) argument 216 rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) argument 231 rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) argument [all...] |
H A D | pcie-xilinx-dma-pl.c | 169 unsigned int devfn, int where) 176 return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 168 xilinx_pl_dma_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) argument
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H A D | pcie-xilinx-nwl.c | 234 * @where: Offset from base 240 int where) 247 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 239 nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) argument
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H A D | pcie-xilinx.c | 172 * @where: Offset from base 178 unsigned int devfn, int where) 185 return pcie->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 177 xilinx_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) argument
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