Searched refs:init (Results 151 - 175 of 9380) sorted by relevance

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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
H A Dhubgk208.fuc536 bra #init
H A Dhubgm107.fuc536 bra #init
/linux-master/drivers/gpu/drm/nouveau/dispnv50/
H A Doimm.c32 int (*init)(struct nouveau_drm *, s32, struct nv50_wndw *);
50 return oimms[cid].init(drm, oimms[cid].oclass, wndw);
H A Dwimm.c32 int (*init)(struct nouveau_drm *, s32, struct nv50_wndw *);
48 return wimms[cid].init(drm, wimms[cid].oclass, wndw);
/linux-master/drivers/clk/hisilicon/
H A Dclkgate-separated.c91 struct clk_init_data init; local
97 init.name = name;
98 init.ops = &clkgate_separated_ops;
99 init.flags = flags;
100 init.parent_names = (parent_name ? &parent_name : NULL);
101 init.num_parents = (parent_name ? 1 : 0);
106 sclk->hw.init = &init;
/linux-master/drivers/clk/mxs/
H A Dclk-div.c75 struct clk_init_data init; local
81 init.name = name;
82 init.ops = &clk_div_ops;
83 init.flags = CLK_SET_RATE_PARENT;
84 init.parent_names = (parent_name ? &parent_name: NULL);
85 init.num_parents = (parent_name ? 1 : 0);
95 div->divider.hw.init = &init;
/linux-master/drivers/clk/rockchip/
H A Dclk-inverter.c78 struct clk_init_data init; local
86 init.name = name;
87 init.num_parents = num_parents;
88 init.flags = CLK_SET_RATE_PARENT;
89 init.parent_names = parent_names;
90 init.ops = &rockchip_inv_clk_ops;
92 inv_clock->hw.init = &init;
H A Dclk-muxgrf.c62 struct clk_init_data init; local
74 init.name = name;
75 init.flags = flags;
76 init.num_parents = num_parents;
77 init.parent_names = parent_names;
78 init.ops = &rockchip_muxgrf_clk_ops;
80 muxgrf_clock->hw.init = &init;
/linux-master/drivers/clk/tegra/
H A Dclk-periph-fixed.c80 struct clk_init_data init; local
91 init.name = name;
92 init.flags = flags;
93 init.parent_names = parent ? &parent : NULL;
94 init.num_parents = parent ? 1 : 0;
95 init.ops = &tegra_clk_periph_fixed_ops;
103 fixed->hw.init = &init;
H A Dclk-pll-out.c94 struct clk_init_data init; local
100 init.name = name;
101 init.ops = &tegra_clk_pll_out_ops;
102 init.parent_names = (parent_name ? &parent_name : NULL);
103 init.num_parents = (parent_name ? 1 : 0);
104 init.flags = flags;
112 /* Data in .init is copied by clk_register(), so stack variable OK */
113 pll_out->hw.init = &init;
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
H A Dinit.h23 struct nvbios_init init = { \
32 nvbios_exec(&init); \
/linux-master/drivers/clk/imx/
H A Dclk-fixup-div.c94 struct clk_init_data init; local
104 init.name = name;
105 init.ops = &clk_fixup_div_ops;
106 init.flags = CLK_SET_RATE_PARENT;
107 init.parent_names = parent ? &parent : NULL;
108 init.num_parents = parent ? 1 : 0;
114 fixup_div->divider.hw.init = &init;
H A Dclk-cpu.c79 struct clk_init_data init; local
91 init.name = name;
92 init.ops = &clk_cpu_ops;
93 init.flags = CLK_IS_CRITICAL;
94 init.parent_names = &parent_name;
95 init.num_parents = 1;
97 cpu->hw.init = &init;
H A Dclk-pllv1.c119 struct clk_init_data init; local
129 init.name = name;
130 init.ops = &clk_pllv1_ops;
131 init.flags = 0;
132 init.parent_names = &parent;
133 init.num_parents = 1;
135 pll->hw.init = &init;
/linux-master/drivers/clk/uniphier/
H A Dclk-uniphier-cpugear.c82 struct clk_init_data init; local
89 init.name = name;
90 init.ops = &uniphier_clk_cpugear_ops;
91 init.flags = CLK_SET_RATE_PARENT;
92 init.parent_names = data->parent_names;
93 init.num_parents = data->num_parents;
98 gear->hw.init = &init;
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
H A Dgf106.c28 .init = g84_pci_init,
34 .pcie.init = gf100_pcie_init,
H A Dg94.c28 .init = g84_pci_init,
34 .pcie.init = g84_pcie_init,
H A Dg92.c36 .init = g84_pci_init,
42 .pcie.init = g84_pcie_init,
/linux-master/drivers/clk/zynqmp/
H A Dclk-gate-zynqmp.c115 struct clk_init_data init; local
122 init.name = name;
123 init.ops = &zynqmp_clk_gate_ops;
125 init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);
127 init.parent_names = parents;
128 init.num_parents = 1;
132 gate->hw.init = &init;
/linux-master/drivers/clk/mmp/
H A Dclk-gate.c99 struct clk_init_data init; local
106 init.name = name;
107 init.ops = &mmp_clk_gate_ops;
108 init.flags = flags;
109 init.parent_names = (parent_name ? &parent_name : NULL);
110 init.num_parents = (parent_name ? 1 : 0);
119 gate->hw.init = &init;
/linux-master/arch/arm/mach-mvebu/
H A Dheadsmp.S19 #include <linux/init.h>
/linux-master/drivers/clk/baikal-t1/
H A Dccu-rst.h51 struct ccu_rst *ccu_rst_hw_register(const struct ccu_rst_init_data *init);
58 struct ccu_rst *ccu_rst_hw_register(const struct ccu_rst_init_data *init) argument
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dgf100.c27 #include <subdev/bios/init.h>
32 gf100_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq) argument
34 struct nvkm_subdev *subdev = &init->subdev;
67 gf100_devinit_disable(struct nvkm_devinit *init) argument
69 struct nvkm_device *device = init->subdev.device;
93 struct nv50_devinit *init = nv50_devinit(base); local
94 struct nvkm_subdev *subdev = &init->base.subdev;
107 .init = nv50_devinit_init,
/linux-master/drivers/clk/socfpga/
H A Dclk-pll.c81 struct clk_init_data init; local
99 init.name = clk_name;
100 init.ops = ops;
101 init.flags = 0;
103 init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
104 init.parent_names = parent_name;
105 pll_clk->hw.hw.init = &init;
H A Dclk-pll-a10.c74 struct clk_init_data init; local
93 init.name = clk_name;
94 init.ops = ops;
95 init.flags = 0;
100 init.num_parents = i;
101 init.parent_names = parent_name;
102 pll_clk->hw.hw.init = &init;

Completed in 197 milliseconds

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