Searched refs:regs (Results 101 - 125 of 167) sorted by relevance

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/haiku/src/add-ons/accelerants/intel_810/
H A Daccelerant.cpp78 gInfo.regsArea = clone_area("i810 regs area", (void**)&(gInfo.regs),
95 gInfo.regs = 0;
H A Daccelerant.h33 uint8* regs; // base address of MMIO register area member in struct:AccelerantInfo
/haiku/src/add-ons/accelerants/radeon/
H A DEngineManagment.c86 OUTREG( ai->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL);
87 OUTREG( ai->regs, RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN |
211 /*if( (int32)(INREG( ai->regs, RADEON_SCRATCH_REG0 ) - st->counter) >= 0 )
239 st->counter, /*INREG( ai->regs, RADEON_SCRATCH_REG0 )*/
H A Ddriver_wrapper.c34 int slots = INREG( ai->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK;
H A Dradeon_accelerant.h44 vuint8 *regs; // pointer to mapped registers member in struct:accelerator_info
/haiku/src/add-ons/accelerants/s3/
H A Daccel.cpp42 gInfo.regsArea = clone_area("S3 regs area", (void**)&(gInfo.regs),
70 gInfo.regs = 0;
H A Dsavage.h78 #define BCI_GET_PTR vuint32* bci_ptr = ((uint32*)(gInfo.regs + BCI_BUFFER_OFFSET))
/haiku/src/add-ons/kernel/power/cpuidle/intel_cstates/
H A Dintel_cstates.cpp144 if ((cpuid.regs.eax & 0xffff) < sizeof(int32))
150 int32 subStates = (cpuid.regs.edx >> (i * 4)) & 0xf;
/haiku/src/system/kernel/arch/x86/
H A Darch_system_info.cpp109 if (cpuid.regs.eax != 0) {
110 sCPUClockSpeed = cpuid.regs.eax * 1000000LL;
/haiku/src/add-ons/accelerants/skeleton/engine/
H A Dglobals.h5 extern vuint32 *regs;
/haiku/src/tests/system/libroot/posix/
H A Dsignal_test.cpp46 sigHandler(int signal, void *userData, vregs *regs) argument
/haiku/src/add-ons/accelerants/nvidia/engine/
H A Dnv_globals.h6 extern vuint32 *regs;
/haiku/src/add-ons/accelerants/via/engine/
H A Dglobals.h5 extern vuint32 *regs;
/haiku/src/add-ons/kernel/busses/virtio/virtio_mmio/
H A DVirtioDevice.h94 status_t Init(phys_addr_t regs, size_t regsLen, int32 irq, int32 queueCnt);
/haiku/src/system/boot/arch/x86/
H A Darch_cpu.cpp327 && (info.regs.ecx & IA32_FEATURE_EXT_HYPERVISOR) != 0) {
329 const uint32 maxVMM = info.regs.eax;
333 uint64 clockSpeed = uint64(info.regs.eax) * 1000;
334 gTimeConversionFactor = (uint64(1000) << 32) / info.regs.eax;
/haiku/src/add-ons/accelerants/skeleton/
H A DInitAccelerant.c52 regs = si->clone_bugfix_regs;
57 regs_area = clone_area(DRIVER_PREFIX " regs", (void **)&regs, B_ANY_ADDRESS,
83 regs = 0;
/haiku/src/add-ons/accelerants/nvidia/
H A DInitAccelerant.c55 regs = si->clone_bugfix_regs;
60 regs_area = clone_area(DRIVER_PREFIX " regs", (void **)&regs, B_ANY_ADDRESS,
83 regs = 0;
/haiku/src/add-ons/accelerants/matrox/
H A DInitAccelerant.c52 regs = si->clone_bugfix_regs;
57 regs_area = clone_area(DRIVER_PREFIX " regs", (void **)&regs, B_ANY_ADDRESS,
83 regs = 0;
/haiku/src/add-ons/accelerants/via/
H A DInitAccelerant.c53 regs = si->clone_bugfix_regs;
58 regs_area = clone_area(DRIVER_PREFIX " regs", (void **)&regs, B_ANY_ADDRESS,
84 regs = 0;
/haiku/src/system/kernel/arch/riscv64/
H A Darch_int.cpp168 uint64* regs = &frame->ra; local
175 registerNames[i + 0], regs[i + 0],
176 registerNames[i + 1], regs[i + 1],
177 registerNames[i + 2], regs[i + 2],
178 registerNames[i + 3], regs[i + 3]
/haiku/src/kits/mail/
H A Dmail_util.cpp1250 struct re_registers regs; local
1253 regs.num_regs = gNsub;
1254 regs.start = (regoff_t*)malloc(gNsub*sizeof(regoff_t));
1255 regs.end = (regoff_t*)malloc(gNsub*sizeof(regoff_t));
1258 string.Length(), 0, string.Length(), &regs)) >= 0;) {
1264 if (start == regs.start[1])
1265 start = regs.start[2];
1267 string.Remove(start,regs.end[0]-start);
1273 if (regs.end[0] - start <= 1)
1277 free(regs
[all...]
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/
H A Dar5416_misc.c617 ar5416CompareDbgHang(struct ath_hal *ah, const mac_dbg_regs_t *regs, argument
627 if (((regs->dma_dbg_4 >> (5*i)) & 0x1f) ==
632 if (((regs->dma_dbg_5 >> (5*i)) & 0x1f) ==
638 if ((regs->dma_dbg_6 & 0x3) == check->dcu_complete_state)
642 if (((regs->dma_dbg_3 >> 18) & 0xf) == check->qcu_stitch_state)
646 if (((regs->dma_dbg_3 >> 22) & 0xf) == check->qcu_fetch_state)
650 if (((regs->dma_dbg_3 >> 26) & 0x7) == check->qcu_complete_state)
/haiku/headers/private/shared/
H A Dcpu_type.h234 memcpy(name, &nameInfo.regs.eax, 4);
235 memcpy(name + 4, &nameInfo.regs.ebx, 4);
236 memcpy(name + 8, &nameInfo.regs.ecx, 4);
237 memcpy(name + 12, &nameInfo.regs.edx, 4);
/haiku/src/system/boot/platform/efi/arch/riscv64/
H A Darch_mmu.cpp433 MapRange(gKernelArgs.arch_args.uart.regs.start,
434 gKernelArgs.arch_args.uart.regs.start,
435 gKernelArgs.arch_args.uart.regs.size,
437 MapAddrRange(gKernelArgs.arch_args.uart.regs,
/haiku/src/add-ons/kernel/drivers/dvb/cx23882/
H A Ddvb_interface.c118 device->regs_area = map_mem(&device->regs, (addr_t)val,
124 TRACE("mapped registers to %p\n", device->regs);

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