/freebsd-11-stable/contrib/gcc/config/arm/ |
H A D | arm.c | 465 /* The bits in this mask specify which 469 /* The bits in this mask specify which instruction scheduling options should 4090 HOST_WIDE_INT mask, base, index; 4097 mask = (1 << bits) - 1; 4098 base = INTVAL (x) & ~mask; 4099 index = INTVAL (x) & mask; 4104 base |= mask; 4105 index -= mask; 6840 address mask depending on the physical architecture that the program 8420 MASK is the ARM register set mask o 4081 HOST_WIDE_INT mask, base, index; local 8410 print_multi_reg(FILE *stream, const char *instr, unsigned reg, unsigned long mask) argument 9440 unsigned long mask; local 10232 emit_multi_reg_push(unsigned long mask) argument 12135 const unsigned int mask; member in struct:builtin_description 12938 number_of_first_bit_set(unsigned mask) argument 12959 thumb_pushpop(FILE *f, unsigned long mask, int push, int *cfa_offset, unsigned long real_regs) argument 13349 unsigned HOST_WIDE_INT mask = 0xff; local 13487 unsigned long mask = live_regs_mask & 0xff; local 15318 unsigned long mask; local [all...] |
H A D | pr-support.c | 155 /* Pop r4-r15 under mask. */ 178 _uw mask; local 180 mask = (0xff0 >> (7 - (op & 7))) & 0xff0; 182 mask |= (1 << R_LR); 183 if (_Unwind_VRS_Pop (context, _UVRSC_CORE, mask, _UVRSD_UINT32) 197 /* Pop r0-r4 under mask. */ 268 /* Pop iWMMXt wCGR{3,2,1,0} under mask. */
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H A D | unwind-arm.c | 252 _uw mask; local 258 mask = discriminator & 0xffff; 263 if (mask & (1 << i)) 267 if ((mask & (1 << R_SP)) == 0)
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/freebsd-11-stable/contrib/gcc/config/ |
H A D | darwin.h | 946 static long mask; \ 953 mask = ~((long) size - 1); \ 956 page = (char *) (((long) addr) & mask); \ 957 end = (char *) ((((long) (addr + (TARGET_64BIT ? 48 : 40))) & mask) + size); \
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H A D | netbsd.h | 207 static long mask; \ 220 mask = ~((long) size - 1); \ 223 page = (char *) (((long) addr) & mask); \ 224 end = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \
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H A D | openbsd.h | 308 long mask = ~(size-1); \ 309 char *page = (char *) (((long) addr) & mask); \ 310 char *end = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \
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H A D | sol2.h | 207 long mask = ~(size-1); \ 208 char *page = (char *) (((long) addr) & mask); \ 209 char *end = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \
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/freebsd-11-stable/contrib/gcc/config/i386/ |
H A D | i386.c | 8988 /* mask precision exception for nearbyint() */ 9020 /* mask precision exception for nearbyint() */ 9205 int mask; 9208 mask = eflags_p << 3; 9209 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2; 9210 mask |= unordered_p << 1; 9211 mask |= stack_top_dies; 9213 gcc_assert (mask < 16); 9214 ret = alt[mask]; 9796 Create a mask fo 9181 int mask; local 9782 rtx mask; local 9826 rtx mask, set, use, clob, dst, src; local 9894 rtx dest, op0, op1, mask, nmask; local 9948 rtx dest, op0, op1, mask, x; local 9976 rtx dest, scratch, op0, op1, mask, nmask, x; local 12049 rtx t1, t2, mask; local 15004 const unsigned int mask; member in struct:builtin_description [all...] |
/freebsd-11-stable/contrib/gcc/config/ia64/ |
H A D | ia64.c | 134 HARD_REG_SET mask; /* mask of saved registers. */ member in struct:ia64_frame_info 135 unsigned int gr_used_mask; /* mask of registers in use as gr spill 760 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction. 1667 rtx t1, t2, mask; 1674 mask = GEN_INT (-0x80000000); 1675 mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask)); 1676 mask 1662 rtx t1, t2, mask; local 2326 HARD_REG_SET mask; local 3646 int mask, grsave, grsave_prev; local 6687 int mask = 0; local [all...] |
H A D | unwind-ia64.c | 152 unsigned long pr_mask; /* predicate mask */ 256 atomic_alloc (unsigned int *mask) 258 unsigned int old = *mask, ret, new; 266 new = __sync_val_compare_and_swap (mask, old, new); 278 atomic_free (unsigned int *mask, int bit) 280 __sync_xor_and_fetch (mask, 1 << bit); 543 unsigned char kind, mask = 0, *cp = sr->imask; 554 mask = *cp++; 555 kind = (mask >> 2*(3-(t & 3))) & 3; 580 desc_prologue (int body, unw_word rlen, unsigned char mask, 255 atomic_alloc(unsigned int *mask) argument 277 atomic_free(unsigned int *mask, int bit) argument 541 unsigned char kind, mask = 0, *cp = sr->imask; local 578 desc_prologue(int body, unw_word rlen, unsigned char mask, unsigned char grsave, struct unw_state_record *sr) argument 1163 unsigned char byte1, mask, grsave; local 1247 unsigned char mask = (code & 0x0f); local [all...] |
/freebsd-11-stable/contrib/gcc/config/mips/ |
H A D | mips.c | 425 unsigned int mask; /* mask of saved gp registers */ local 426 unsigned int fmask; /* mask of saved fp registers */ 2413 m16_check_op (rtx op, int low, int high, int mask) 2418 && (INTVAL (op) & mask) == 0); 3526 gcc_assert ((cfun->machine->frame.mask >> 31) & 1); 6422 unsigned int mask; /* mask of saved gp registers */ 6423 unsigned int fmask; /* mask of saved fp registers */ 6429 mask 2406 m16_check_op(rtx op, int low, int high, int mask) argument 6388 unsigned int mask; /* mask of saved gp registers */ local [all...] |
/freebsd-11-stable/contrib/gcc/config/rs6000/ |
H A D | darwin-fallback.c | 109 uint32_t mask = 0xF << ((ins >> 21 & 0x1C) ^ 0x1C); local 111 cr |= mask; 113 cr &= ~mask; 204 uint32_t mask = 0; local 206 mask |= ((-(ins >> (12 + i) & 1)) & 0xF) << 4 * i; 207 cr = (cr & ~mask) | (gprs [ins >> 21 & 0x1F] & mask);
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H A D | rs6000.c | 81 unsigned int vrsave_mask; /* mask of vec registers to save */ 262 /* mask is not const because we're going to alter it below. This 265 unsigned int mask; member in struct:builtin_description 2197 unsigned mask = GET_MODE_MASK (inner); 2209 mask >>= bitsize; 2210 if (splat_val != ((small_val << bitsize) | (small_val & mask))) 2486 rtx mask, mem, x; 2502 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16)); 2504 XVECEXP (mask, 0, i) = GEN_INT (i); 2506 /* Set permute mask t 2189 unsigned mask = GET_MODE_MASK (inner); local 2478 rtx mask, mem, x; local 6116 def_builtin(int mask, const char *name, tree type, int code) argument 6582 const unsigned int mask; member in struct:builtin_description_predicates 11707 rtx mask; local 11882 rs6000_emit_vector_select(rtx dest, rtx op1, rtx op2, rtx mask) argument 11911 rtx mask; local 12273 rtx mask; local 12302 rtx mask, xorm; local 12526 rtx addrSI, align, wdst, shift, mask; local 12571 rs6000_split_compare_and_swapqhi(rtx dest, rtx mask, rtx oldval, rtx newval, rtx mem, rtx scratch) argument 12838 unsigned int i, mask = 0; local [all...] |
H A D | spe.h | 1057 __ev_clr_spefscr_field (int mask) argument 1062 i &= ~mask;
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/freebsd-11-stable/contrib/gcc/config/s390/ |
H A D | s390.c | 470 /* If a test-under-mask instruction can be used to implement 663 rtx mask = XEXP (*op0, 1); local 670 && ((INTVAL (mask) 683 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode); 685 *op0 = gen_rtx_AND (QImode, inner, mask); 817 /* Return branch condition mask to implement a branch 1024 int mask = s390_branch_condition_mask (code); local 1025 gcc_assert (mask >= 0); 1028 mask 1274 HOST_WIDE_INT mask; local [all...] |
/freebsd-11-stable/contrib/gcc/config/sparc/ |
H A D | lb1spc.asm | 16 andncc %o4, 0xfff, %o5 ! mask out lower 12 bits
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H A D | sparc.c | 1322 during CSE. We mask out the non-HIGH bits, and matches 8889 rtx memsi, val, mask, end_label, loop_label, cc; 8914 mask = force_reg (SImode, GEN_INT (0xff)); 8916 mask = force_reg (SImode, GEN_INT (0xffff)); 8918 emit_insn (gen_rtx_SET (VOIDmode, mask, 8919 gen_rtx_ASHIFT (SImode, mask, off))); 8922 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask), 8934 gen_rtx_AND (SImode, oldv, mask))); 8937 gen_rtx_AND (SImode, newv, mask))); 8954 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask), 8863 rtx memsi, val, mask, end_label, loop_label, cc; local [all...] |
/freebsd-11-stable/contrib/gcc/cp/ |
H A D | lex.c | 175 /* Disable mask. Keywords are disabled if (reswords[i].disable & mask) is 316 int mask = ((flag_no_asm ? D_ASM : 0) 326 if (! (reswords[i].disable & mask)) 315 int mask = ((flag_no_asm ? D_ASM : 0) local
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H A D | parser.c | 20916 cp_parser_omp_all_clauses (cp_parser *parser, unsigned int mask, 20991 if (((mask >> c_kind) & 1) == 0) 21482 unsigned int mask = OMP_PARALLEL_CLAUSE_MASK; 21490 mask |= OMP_FOR_CLAUSE_MASK; 21491 mask &= ~(1u << PRAGMA_OMP_CLAUSE_NOWAIT); 21502 mask |= OMP_SECTIONS_CLAUSE_MASK; 21503 mask &= ~(1u << PRAGMA_OMP_CLAUSE_NOWAIT); 21507 clauses = cp_parser_omp_all_clauses (parser, mask, p_name, pragma_tok); 20913 cp_parser_omp_all_clauses(cp_parser *parser, unsigned int mask, const char *where, cp_token *pragma_tok) argument 21479 unsigned int mask = OMP_PARALLEL_CLAUSE_MASK; local
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H A D | typeck.c | 3818 HOST_WIDE_INT constant, mask; 3839 mask = (~ (HOST_WIDE_INT) 0) << bits; 3840 if ((mask & constant) != mask) 3811 HOST_WIDE_INT constant, mask; local
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/freebsd-11-stable/contrib/gcc/ |
H A D | df-core.c | 361 df_set_flags (struct dataflow *dflow, int mask) argument 365 gcc_assert (!(mask & (~dflow->problem->changeable_flags))); 367 dflow->flags |= mask; 376 df_clear_flags (struct dataflow *dflow, int mask) argument 380 gcc_assert (!(mask & (~dflow->problem->changeable_flags))); 382 dflow->flags &= !mask;
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H A D | dojump.c | 255 HOST_WIDE_INT mask = (HOST_WIDE_INT) 1 258 build_int_cst_type (argtype, mask)), 254 HOST_WIDE_INT mask = (HOST_WIDE_INT) 1 local
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H A D | double-int.c | 27 /* Returns mask for PREC bits. */ 33 double_int mask; local 39 mask.high = (HOST_WIDE_INT) m; 40 mask.low = ALL_ONES; 44 mask.high = 0; 45 mask.low = ((unsigned HOST_WIDE_INT) 2 << (prec - 1)) - 1; 48 return mask; 72 double_int mask = double_int_mask (prec); local 75 r.low = cst.low & mask.low; 76 r.high = cst.high & mask 86 double_int mask = double_int_mask (prec); local [all...] |
H A D | expmed.c | 1784 mask out the upper bits. */ 1826 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value 1828 complement of that if COMPLEMENT. The mask is truncated if 1829 necessary to the width of mode MODE. The mask is zero-extended if 3344 unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1; 3345 *multiplier_ptr = GEN_INT (mhigh_lo & mask); 3346 return mhigh_lo >= mask; 3367 unsigned HOST_WIDE_INT mask; 3371 mask = (n == HOST_BITS_PER_WIDE_INT 3377 y = y * (2 - x*y) & mask; /* Modul 3332 unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1; local 3355 unsigned HOST_WIDE_INT mask; local 4778 rtx abs_rem, abs_op1, tem, mask; local [all...] |
H A D | expr.c | 1298 here because if SIZE is less than the mode mask, as it is 1300 actual mode mask. */ 2675 the mode mask, as it is returned by the macro, it will 2676 definitely be less than the actual mode mask. */ 4013 rtx mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << bitsize) 4015 value = expand_and (GET_MODE (str_rtx), value, mask, 5552 implies a mask operation. If the precision is the same size as 5553 the field we're storing into, that mask is redundant. This is 7413 we must mask only the number of bits in the bitfield, 8870 rtx mask; 4001 rtx mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << bitsize) local 8849 rtx mask; local [all...] |