| /u-boot/arch/arm/include/asm/arch-tegra/ |
| H A D | clock.h | 117 * Reset a peripheral. This puts it in reset, waits for a delay, then takes
118 * it out of reset and waits for th delay again.
120 * @param periph_id peripheral to reset
126 * Put a peripheral into or out of reset.
128 * @param periph_id peripheral to reset
129 * @param enable 1 to put into reset, 0 to take out of reset
136 /* Things we can hold in reset for each CPU */
144 * Put parts of the CPU complex into or out of reset.\
148 * @param reset
[all...] |
| /u-boot/drivers/net/ |
| H A D | xilinx_axi_mrmac.h | 46 u32 reset; /* 0x4: Reset Register */ member in struct:mrmac_regs
87 #define MRMAC_DMARST_TIMEOUT 500 /* MCDMA reset timeout in msecs */
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| /u-boot/drivers/watchdog/ |
| H A D | sunxi_wdt.c | 79 /* Set system reset function */
122 .reset = sunxi_wdt_reset,
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| /u-boot/include/ |
| H A D | ahci.h | 39 #define HOST_RESET (1 << 0) /* reset controller; self-clear */
174 * reset() - reset the controller
176 * @dev: Controller to reset
179 int (*reset)(struct udevice *dev); member in struct:ahci_ops
184 * @dev: Controller to reset
202 * sata_reset() - reset the controller
204 * @dev: Controller to reset
212 * @dev: Controller to reset
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| H A D | miiphy.h | 142 * @reset: Reset the MDIO bus, NULL if not supported
148 int (*reset)(struct udevice *mdio_dev); member in struct:mdio_ops
183 * dm_mdio_reset - Wrapper over .reset() operation for DM MDIO
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| /u-boot/arch/arm/cpu/armv7/ |
| H A D | start.S | 24 * Startup Code (reset vector)
32 .globl reset
39 reset: label
49 adr r0, reset /* r0 <- Runtime value of reset label */
50 ldr r1, =reset /* r1 <- Linked value of reset label */
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| /u-boot/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 408 * DDR memory sanity checking failed, tally and do hard reset
414 register u32 reset; local
422 /* We have to execute the reset function from cache. Indeed,
427 * the NOR, which is why the reset instructions are prefetched
433 * The last instruction in _machine_restart() will reset the
435 * from the reset vector.
437 reset = KSEG0ADDR(_machine_restart);
438 icache_lock((void *)reset, 128);
439 asm volatile ("jr %0"::"r" (reset));
452 /* DDR has reset pi
[all...] |
| /u-boot/arch/arm/lib/ |
| H A D | Makefile | 77 obj-y += reset.o
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| /u-boot/drivers/phy/qcom/ |
| H A D | phy-qcom-snps-femto-v2.c | 14 #include <reset.h>
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| /u-boot/test/dm/ |
| H A D | Makefile | 101 obj-$(CONFIG_DM_RESET) += reset.o
119 obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o
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| /u-boot/drivers/clk/sunxi/ |
| H A D | clk_a83t.c | 13 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
|
| H A D | clk_a31.c | 13 #include <dt-bindings/reset/sun6i-a31-ccu.h>
|
| H A D | clk_a80.c | 13 #include <dt-bindings/reset/sun9i-a80-ccu.h>
|
| H A D | clk_a23.c | 13 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
|
| H A D | clk_d1.c | 12 #include <dt-bindings/reset/sun20i-d1-ccu.h>
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| /u-boot/drivers/phy/ |
| H A D | bcm6368-usbh-phy.c | 17 #include <reset.h>
155 /* perform reset */
|
| H A D | meson-gxbb-usb2.c | 16 #include <reset.h>
102 /* reset the PHY */
169 pr_err("Failed to deassert reset\n");
|
| H A D | phy-rcar-gen2.c | 15 #include <reset.h>
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| /u-boot/drivers/power/domain/ |
| H A D | apple-pmgr.c | 13 #include <reset-uclass.h>
|
| /u-boot/drivers/soc/ti/ |
| H A D | pruss.c | 13 #include <reset.h>
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| /u-boot/drivers/remoteproc/ |
| H A D | ti_k3_arm64_rproc.c | 15 #include <reset.h>
32 * @rproc_rst: rproc reset control data
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| /u-boot/drivers/rtc/ |
| H A D | isl1208.c | 181 .reset = isl1208_rtc_reset,
|
| H A D | pcf2127.c | 117 .reset = pcf2127_rtc_reset,
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| H A D | mvrtc.c | 162 .reset = mv_rtc_reset,
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| /u-boot/arch/arm/mach-socfpga/ |
| H A D | misc_gen5.c | 29 #include <dt-bindings/reset/altr,rst-mgr.h>
194 * issuing warm reset. The ancient kernel code expects this
|