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/u-boot/drivers/spi/
H A Dspi-aspeed-smc.c117 /* keep in default value */
481 * CS in order to avoid affecting the default boot up sequence
610 * if flash is in 4-byte address mode.
649 aspeed_spi_read_from_ahb(flash->ahb_base, op->data.buf.in,
923 * in order to get device (SPI NOR flash) information
/u-boot/drivers/mtd/spi/
H A Dspi-nor-core.c54 u8 length; /* in double words */
278 /* 2 bytes per clock cycle in DTR mode. */
291 op->data.buf.in = buf;
351 * We don't want to read only one byte in DTR mode. So, read 2 and then
408 op.data.buf.in);
424 op.data.buf.in += op.data.nbytes;
465 * Read the status register, returning its value in the location
492 * We don't want to read only one byte in DTR mode. So, read 2 and then
508 * Read the flag status register, returning its value in the location
535 * We don't want to read only one byte in DT
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