Searched refs:cache (Results 76 - 100 of 359) sorted by relevance
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/u-boot/arch/arm/mach-versal-net/ |
H A D | cpu.c | 12 #include <asm/cache.h> 17 #include <asm/cache.h>
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/u-boot/arch/arm/cpu/armv7/ |
H A D | psci.S | 176 mov r10, #0 @ start clean at cache level 0 178 add r2, r10, r10, lsr #1 @ work out 3x current cache level 179 mov r1, r0, lsr r2 @ extract cache type bits from clidr 180 and r1, r1, #7 @ mask of the bits for current cache only 181 cmp r1, #2 @ see what cache we have at this level 182 blt skip @ skip if no cache, or just i-cache 184 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 188 and r2, r1, #7 @ extract the length of the cache lines 198 orr r11, r10, r4, lsl r5 @ factor way and cache numbe [all...] |
/u-boot/arch/arm/lib/ |
H A D | Makefile | 51 obj-$(CONFIG_$(SPL_TPL_)SYS_L2_PL310) += cache-pl310.o 80 obj-y += cache.o 81 obj-$(CONFIG_SYS_ARM_CACHE_CP15) += cache-cp15.o
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/u-boot/arch/arm/mach-omap2/ |
H A D | Makefile | 31 obj-y += omap-cache.o
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/u-boot/arch/arm/mach-tegra/ |
H A D | Makefile | 17 obj-y += cache.o
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/u-boot/arch/arm/mach-versal/ |
H A D | cpu.c | 10 #include <asm/cache.h> 15 #include <asm/cache.h>
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/u-boot/arch/powerpc/include/asm/ |
H A D | ppc.h | 129 #include <asm/cache.h>
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/u-boot/arch/powerpc/lib/ |
H A D | ppccache.S | 13 #include <asm/cache.h> 61 * Write any modified data cache blocks out to memory and invalidate them. 62 * Does not invalidate the corresponding instruction cache blocks. 84 * Like above, but invalidate the D-cache. This is used by the 8xx 85 * to invalidate the cache so the PPC core doesn't get stale data 86 * from the CPM (no cache snooping here :-).
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/u-boot/arch/sandbox/cpu/ |
H A D | Makefile | 8 obj-y := cache.o cpu.o state.o
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/u-boot/arch/arm/cpu/armv8/ |
H A D | fwcall.c | 10 #include <asm/cache.h>
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H A D | Makefile | 14 obj-y += cache.o
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/u-boot/board/synopsys/axs10x/ |
H A D | axs10x.c | 13 #include <asm/cache.h>
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/u-boot/arch/mips/include/asm/ |
H A D | cacheops.h | 3 * Cache operations for the cache instruction. 11 #include <asm/cache.h> 21 __asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr)); 30 /* Prefetch and lock instructions into cache */ 36 asm volatile (" cache %0, %1(%2)"
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/u-boot/arch/microblaze/cpu/ |
H A D | cache.c | 10 #include <asm/cache.h>
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/u-boot/arch/arc/lib/ |
H A D | bootm.c | 12 #include <asm/cache.h>
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/u-boot/board/freescale/common/ |
H A D | mpc85xx_sleep.c | 7 #include <asm/cache.h>
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/u-boot/include/ |
H A D | memalign.h | 10 * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It 15 #include <asm/cache.h> 22 * the cache before and after a read and/or write operation is required for 67 * of a function scoped static buffer. It can not be used to create a cache 98 * malloc_cache_aligned() - allocate a memory region aligned to cache line size 100 * This allocates memory at a cache-line boundary. The amount allocated may 102 * cache-line size. This ensured that subsequent cache operations on this
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/u-boot/drivers/crypto/fsl/ |
H A D | rng.c | 9 #include <asm/cache.h>
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/u-boot/drivers/fpga/ |
H A D | versalpl.c | 14 #include <asm/cache.h>
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/u-boot/arch/arm/mach-mediatek/mt8512/ |
H A D | init.c | 19 #include <asm/cache.h>
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/u-boot/arch/arm/mach-mediatek/mt8518/ |
H A D | init.c | 18 #include <asm/cache.h>
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/u-boot/arch/arm/mach-mvebu/ |
H A D | arm64-common.c | 10 #include <asm/cache.h>
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/u-boot/drivers/video/ |
H A D | bcm2835.c | 12 #include <asm/cache.h>
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/u-boot/drivers/cache/ |
H A D | cache-sifive-ccache.c | 7 #include <cache.h> 28 /* Enable all ways of composable cache */
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/u-boot/drivers/bootcount/ |
H A D | bootcount_ram.c | 9 #include <asm/cache.h>
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