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/u-boot/arch/arm/mach-versal-net/
H A Dcpu.c12 #include <asm/cache.h>
17 #include <asm/cache.h>
/u-boot/arch/arm/cpu/armv7/
H A Dpsci.S176 mov r10, #0 @ start clean at cache level 0
178 add r2, r10, r10, lsr #1 @ work out 3x current cache level
179 mov r1, r0, lsr r2 @ extract cache type bits from clidr
180 and r1, r1, #7 @ mask of the bits for current cache only
181 cmp r1, #2 @ see what cache we have at this level
182 blt skip @ skip if no cache, or just i-cache
184 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
188 and r2, r1, #7 @ extract the length of the cache lines
198 orr r11, r10, r4, lsl r5 @ factor way and cache numbe
[all...]
/u-boot/arch/arm/lib/
H A DMakefile51 obj-$(CONFIG_$(SPL_TPL_)SYS_L2_PL310) += cache-pl310.o
80 obj-y += cache.o
81 obj-$(CONFIG_SYS_ARM_CACHE_CP15) += cache-cp15.o
/u-boot/arch/arm/mach-omap2/
H A DMakefile31 obj-y += omap-cache.o
/u-boot/arch/arm/mach-tegra/
H A DMakefile17 obj-y += cache.o
/u-boot/arch/arm/mach-versal/
H A Dcpu.c10 #include <asm/cache.h>
15 #include <asm/cache.h>
/u-boot/arch/powerpc/include/asm/
H A Dppc.h129 #include <asm/cache.h>
/u-boot/arch/powerpc/lib/
H A Dppccache.S13 #include <asm/cache.h>
61 * Write any modified data cache blocks out to memory and invalidate them.
62 * Does not invalidate the corresponding instruction cache blocks.
84 * Like above, but invalidate the D-cache. This is used by the 8xx
85 * to invalidate the cache so the PPC core doesn't get stale data
86 * from the CPM (no cache snooping here :-).
/u-boot/arch/sandbox/cpu/
H A DMakefile8 obj-y := cache.o cpu.o state.o
/u-boot/arch/arm/cpu/armv8/
H A Dfwcall.c10 #include <asm/cache.h>
H A DMakefile14 obj-y += cache.o
/u-boot/board/synopsys/axs10x/
H A Daxs10x.c13 #include <asm/cache.h>
/u-boot/arch/mips/include/asm/
H A Dcacheops.h3 * Cache operations for the cache instruction.
11 #include <asm/cache.h>
21 __asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
30 /* Prefetch and lock instructions into cache */
36 asm volatile (" cache %0, %1(%2)"
/u-boot/arch/microblaze/cpu/
H A Dcache.c10 #include <asm/cache.h>
/u-boot/arch/arc/lib/
H A Dbootm.c12 #include <asm/cache.h>
/u-boot/board/freescale/common/
H A Dmpc85xx_sleep.c7 #include <asm/cache.h>
/u-boot/include/
H A Dmemalign.h10 * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It
15 #include <asm/cache.h>
22 * the cache before and after a read and/or write operation is required for
67 * of a function scoped static buffer. It can not be used to create a cache
98 * malloc_cache_aligned() - allocate a memory region aligned to cache line size
100 * This allocates memory at a cache-line boundary. The amount allocated may
102 * cache-line size. This ensured that subsequent cache operations on this
/u-boot/drivers/crypto/fsl/
H A Drng.c9 #include <asm/cache.h>
/u-boot/drivers/fpga/
H A Dversalpl.c14 #include <asm/cache.h>
/u-boot/arch/arm/mach-mediatek/mt8512/
H A Dinit.c19 #include <asm/cache.h>
/u-boot/arch/arm/mach-mediatek/mt8518/
H A Dinit.c18 #include <asm/cache.h>
/u-boot/arch/arm/mach-mvebu/
H A Darm64-common.c10 #include <asm/cache.h>
/u-boot/drivers/video/
H A Dbcm2835.c12 #include <asm/cache.h>
/u-boot/drivers/cache/
H A Dcache-sifive-ccache.c7 #include <cache.h>
28 /* Enable all ways of composable cache */
/u-boot/drivers/bootcount/
H A Dbootcount_ram.c9 #include <asm/cache.h>

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