Searched refs:CFG_SYS_SDRAM_BASE (Results 26 - 50 of 556) sorted by relevance

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/u-boot/include/configs/
H A Dci20.h14 #define CFG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ macro
H A Dap121.h9 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A Dexynos5250-common.h12 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
H A Dhighbank.h17 #define CFG_SYS_SDRAM_BASE 0x00000000 macro
H A D10m50_devboard.h33 #define CFG_SYS_SDRAM_BASE 0xc8000000 macro
H A D3c120_devboard.h29 #define CFG_SYS_SDRAM_BASE 0xD0000000 macro
H A Dsama7g5ek.h15 #define CFG_SYS_SDRAM_BASE 0x60000000 macro
H A Dmt7629.h16 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
H A Dmt7620.h11 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A Dkstr-sama5d27.h12 #define CFG_SYS_SDRAM_BASE 0x20000000 macro
H A Dsifive-unmatched.h14 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A Dpe2201.h14 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 macro
H A Docteontx2_common.h13 #define CFG_SYS_SDRAM_BASE CONFIG_TEXT_BASE macro
H A Dsmdkv310.h14 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
26 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
28 #define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
30 #define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
32 #define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
H A Dexynos78x0-common.h24 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
27 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
29 #define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
31 #define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
33 #define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
35 #define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
37 #define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
39 #define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
41 #define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
43 #define PHYS_SDRAM_9 (CFG_SYS_SDRAM_BASE
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H A Dmalta.h22 # define CFG_SYS_SDRAM_BASE 0xffffffff80000000 macro
24 # define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A Dorigen.h14 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
15 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
H A Dexynos7420-common.h22 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
24 #define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
26 #define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
28 #define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
30 #define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
32 #define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
34 #define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
36 #define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
H A Dbmips_bcm63268.h12 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A Dbmips_bcm6328.h12 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A Dbmips_bcm6318.h12 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A Dbmips_bcm6362.h12 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A Dbmips_bcm6838.h12 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A Dintegrator-common.h33 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 macro
H A Docteon_common.h17 #define CFG_SYS_SDRAM_BASE 0xffffffff80000000 macro

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