Searched refs:PTR (Results 51 - 62 of 62) sorted by relevance
123
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/mips/kernel/ |
H A D | r4k_fpu.S | 28 PTR .ex\@, fault
|
H A D | irix5sys.S | 1035 PTR \function
|
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/sound/pci/ca0106/ |
H A D | ca0106.h | 75 #define PTR 0x00 /* Indexed register set pointer register */ macro 94 #define IPR_AI 0x00000100 /* Audio pending register changed. See PTR reg 0x76 */ 114 #define INTE_AI 0x00000100 /* Audio pending register changed. See PTR reg 0x75 */ 173 /* CA0106 pointer-offset register set, accessed through the PTR and DATA registers */ 187 /* PTR[5:0], Default: 0x0 */
|
H A D | ca0106_main.c | 294 outl(regptr, emu->port + PTR); 311 outl(regptr, emu->port + PTR);
|
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/mips/lib/ |
H A D | memcpy-inatomic.S | 90 PTR 9b, handler; \
|
H A D | memcpy.S | 90 PTR 9b, handler; \
|
H A D | csum_partial.S | 316 PTR 9b, handler; \
|
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/sound/oss/emu10k1/ |
H A D | 8010.h | 56 #define PTR 0x00 /* Indexed register set pointer register */ macro 248 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
|
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/sound/pci/emu10k1/ |
H A D | emu10k1x.c | 69 #define PTR 0x00 /* Indexed register set pointer register */ macro 108 /* Emu10k1x pointer-offset register set, accessed through the PTR and DATA registers */ 306 outl(regptr, emu->port + PTR); 323 outl(regptr, emu->port + PTR);
|
/netgear-WNDR4500-V1.0.1.40_1.0.68/ap/gpl/timemachine/openssl-0.9.8e/crypto/engine/ |
H A D | eng_padlock.c | 537 bt DWORD PTR[esp],30 local
|
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/sound/ |
H A D | emu10k1.h | 65 #define PTR 0x00 /* Indexed register set pointer register */ macro 367 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
|
/netgear-WNDR4500-V1.0.1.40_1.0.68/ap/gpl/timemachine/libiconv-1.11/ |
H A D | configure | 26952 *32 | PTR | MAX | PTRDIFF) widthlist="32 64" ;; 27069 *32 | PTR | MAX | PTRDIFF) widthlist="32 64" ;; 27186 *32 | PTR | MAX | PTRDIFF) widthlist="32 64" ;; 27308 *32 | PTR | MAX | PTRDIFF) widthlist="32 64" ;; 27424 *32 | PTR | MAX | PTRDIFF) widthlist="32 64" ;; [all...] |
Completed in 298 milliseconds
123