/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/minidlna/ffmpeg-2.3.4/libavcodec/arm/ |
H A D | vc1dsp_neon.S | 176 vadd.i16 q10, q14, q15 @ t5|t6 = old t1|t2 + old t3|t4 196 @ t6 d21 202 vadd.i16 q3, q15, q10 @ line[7,6] = t5|t6 + 1 209 vhadd.s16 q0, q8, q10 @ line[0,1] = (t1|t2 + t5|t6) >> 1 212 vhsub.s16 q3, q3, q8 @ line[7,6] = (t5|t6 - t1|t2 + 1) >> 1 215 vhsub.s16 q3, q10, q8 @ line[7,6] = (t5|t6 - t1|t2) >> 1 296 @ Compute t5, t6, t7, t8 from old t1, t2, t3, t4. Actually, it computes 297 @ half of t5, t6, t7, t8 since t1, t2, t3, t4 are halved. 300 vadd.i16 q13, q12, q2 @ t6 = t2 + t4
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H A D | fft_neon.S | 83 vadd.f32 d25, d25, d27 @ a3r-a3i,a3i+a3r t5,t6 127 vadd.f32 q11, q12, q1 @ {t1a,t2a,t5,t6} 144 vadd.f32 q0, q12, q13 @ {t1,t2,t5,t6} 152 vswp d1, d26 @ q0{t1,t2,t3,t4} q13{t6,t5,t7,t8} 184 vmla.f32 q13, q0, d5[0] @ {t1,t2,t5,t6} 258 vmla.f32 q10, q0, d5[1] @ {t1,t2,t5,t6}
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/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/minidlna/ffmpeg-2.3.4/libavcodec/ |
H A D | vp9dsp.c | 938 int t0, t0a, t1, t1a, t2, t2a, t3, t3a, t4, t4a, t5, t5a, t6, t6a, t7, t7a; local 959 t6 = ((t6a + t5a) * 11585 + (1 << 13)) >> 14; 962 out[1] = t1 + t6; 967 out[6] = t1 - t6; 974 int t0, t0a, t1, t1a, t2, t2a, t3, t3a, t4, t4a, t5, t5a, t6, t6a, t7, t7a; local 991 t6 = (t2a - t6a + (1 << 13)) >> 14; 996 t6a = 15137 * t7 - 6270 * t6; 997 t7a = 6270 * t7 + 15137 * t6; 1006 t6 = (t4a - t6a + (1 << 13)) >> 14; 1011 out[2] = ((t6 1020 int t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15; local 1108 int t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15; local 1252 int t6 = t7a - t6a; local [all...] |
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/timemachine/db-4.7.25.NC/test/scr015/ |
H A D | TestConstruct01.cpp | 227 void t6(int except_flag) function 283 t6(except_flag);
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/ia64/lib/ |
H A D | memcpy_mck.S | 48 #define t6 t2 // alias! define 54 #define t12 t6 // alias! 235 EX(.ex_handler, (p[D]) ld8 t6 = [src0], 3*8) 242 EX(.ex_handler, (p[D]) st8 [dst0] = t6, 3*8) 437 EK(.ex_handler_short, (p8) ld1 t6=[src1],2) 442 EK(.ex_handler_short, (p8) st1 [dst1]=t6,2) 484 EX(.ex_handler_short, (p11) ld1 t6=[src1],2) 491 EX(.ex_handler_short, (p11) st1 [dst1] = t6,2)
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/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/iserver/libav-0.8.8/libavcodec/ppc/ |
H A D | vc1dsp_altivec.c | 43 t6 = vec_sub(t1, t3); \ 68 s2 = vec_add(t6, t2); \ 71 s5 = vec_sub(t6, t2); \ 138 vector signed int t0, t1, t2, t3, t4, t5, t6, t7; local 233 vector signed int t0, t1, t2, t3, t4, t5, t6, t7; local
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/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/minidlna/ffmpeg-2.3.4/libavcodec/ppc/ |
H A D | vc1dsp_altivec.c | 47 t6 = vec_sub(t1, t3); \ 72 s2 = vec_add(t6, t2); \ 75 s5 = vec_sub(t6, t2); \ 142 vector signed int t0, t1, t2, t3, t4, t5, t6, t7; local 237 vector signed int t0, t1, t2, t3, t4, t5, t6, t7; local
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/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/minidlna/ffmpeg-2.3.4/libavcodec/x86/ |
H A D | h264_deblock_10bit.asm | 542 mova t6, t0 ; q2 556 mova t6, t2 ; q2 746 LUMA_INTRA_INTER t4, t5, t6, [r4+r1], [r0+r1*2] 749 LUMA_INTRA_P012 m2, m3, t3, [r0+r5], m1, m0, t5, t6, [pw_2], [r0], [r0+r1], [r0+2*r1] 776 LUMA_INTRA_INTER t8, t9, t10, t5, t6 779 mova t3, t6 ; q2 780 LUMA_INTRA_P012 m2, m3, t3, t7, m1, m0, t9, t10, [pw_2], m4, t6, m5 786 mova m6, t6
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H A D | h264_deblock.asm | 802 lea t6, [r1*3] 804 add r0, t6 808 %define t6 r6 842 TRANSPOSE4x8_LOAD bw, wd, dq, PASS8ROWS(t5, r0, r1, t6) 852 TRANSPOSE8x4B_STORE PASS8ROWS(t5, r0, r1, t6) 881 %define t6 r5 902 TRANSPOSE4x8_LOAD bw, wd, dq, PASS8ROWS(t5, r0, r1, t6) 904 TRANSPOSE8x4B_STORE PASS8ROWS(t5, r0, r1, t6)
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H A D | fft.asm | 104 pfadd %5, %4 ; {t6,t5} 155 addps %1, %1, %2 ; {t1,t2,t6,t5} 157 shufps %2, %1, %3, 0xbe ; {t6,t5,t7,t8} 183 subps %3, %6, %4 ; {t6,t5,tc,tb} 185 shufps %5, %6, %3, 0x8d ; {t2,ta,t6,tc} 227 addps m3, m5, m0 ; t6 273 addps m5, m5, m0 ; t6
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/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/iserver/libav-0.8.8/libavcodec/x86/ |
H A D | h264_deblock_10bit.asm | 541 mova t6, t0 ; q2 555 mova t6, t2 ; q2 740 LUMA_INTRA_INTER t4, t5, t6, [r4+r1], [r0+r1*2] 743 LUMA_INTRA_P012 m2, m3, t3, [r0+r5], m1, m0, t5, t6, [pw_2], [r0], [r0+r1], [r0+2*r1] 769 LUMA_INTRA_INTER t8, t9, t10, t5, t6 772 mova t3, t6 ; q2 773 LUMA_INTRA_P012 m2, m3, t3, t7, m1, m0, t9, t10, [pw_2], m4, t6, m5 779 mova m6, t6
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H A D | fft_mmx.asm | 100 pfadd %5, %4 ; {t6,t5} 150 addps %1, %1, %2 ; {t1,t2,t6,t5} 152 shufps %2, %1, %3, 0xbe ; {t6,t5,t7,t8} 178 subps %3, %6, %4 ; {t6,t5,tc,tb} 180 shufps %5, %6, %3, 0x8d ; {t2,ta,t6,tc} 222 addps m3, m5, m0 ; t6 268 addps m5, m5, m0 ; t6
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H A D | h264_deblock.asm | 801 lea t6, [r1*3] 803 add r0, t6 807 %define t6 r6 835 TRANSPOSE4x8_LOAD bw, wd, dq, PASS8ROWS(t5, r0, r1, t6) 841 TRANSPOSE8x4B_STORE PASS8ROWS(t5, r0, r1, t6) 867 %define t6 r5 888 TRANSPOSE4x8_LOAD bw, wd, dq, PASS8ROWS(t5, r0, r1, t6) 890 TRANSPOSE8x4B_STORE PASS8ROWS(t5, r0, r1, t6)
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/netgear-R7000-V1.0.7.12_1.2.5/src/shared/ |
H A D | bcmstdlib.c | 656 uint32 t1, t2, t3, t4, t5, t6, t7, t8; local 678 "=r" (t3), "=r" (t4), "=r" (t5), "=r" (t6), "=r" (t7), 730 "=r" (t3), "=r" (t4), "=r" (t5), "=r" (t6) 738 "=r" (t3), "=r" (t4), "=r" (t5), "=r" (t6),
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H A D | sbsdram.S | 94 * t6: retaddr - - - 125 move t6,ra 142 jr t6 605 jr t6 622 jr t6 630 jr t6
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H A D | aisdram.S | 228 move t6,ra 275 jr t6 288 jr t6 # Return with 0 rc. 515 jr t6 954 3: jr t6
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sparc/lib/ |
H A D | checksum_32.S | 190 #define CSUMCOPY_BIGCHUNK_ALIGNED(src, dst, sum, off, t0, t1, t2, t3, t4, t5, t6, t7) \ 196 ldd [src + off + 0x18], t6; \ 204 std t6, [dst + off + 0x18]; \ 205 addxcc t6, sum, sum; \ 212 #define CSUMCOPY_BIGCHUNK(src, dst, sum, off, t0, t1, t2, t3, t4, t5, t6, t7) \ 216 ldd [src + off + 0x18], t6; \ 229 st t6, [dst + off + 0x18]; \ 230 addxcc t6, sum, sum; \
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H A D | copy_user.S | 66 #define MOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ 70 ldd [%src + (offset) + 0x18], %t6; \ 77 st %t6, [%dst + (offset) + 0x18]; \ 80 #define MOVE_BIGALIGNCHUNK(src, dst, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ 84 ldd [%src + (offset) + 0x18], %t6; \ 88 std %t6, [%dst + (offset) + 0x18];
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/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/iserver/libav-0.8.8/libavcodec/arm/ |
H A D | fft_neon.S | 83 vadd.f32 d25, d25, d27 @ a3r-a3i,a3i+a3r t5,t6 127 vadd.f32 q11, q12, q1 @ {t1a,t2a,t5,t6} 144 vadd.f32 q0, q12, q13 @ {t1,t2,t5,t6} 152 vswp d1, d26 @ q0{t1,t2,t3,t4} q13{t6,t5,t7,t8} 184 vmla.f32 q13, q0, d5[0] @ {t1,t2,t5,t6} 258 vmla.f32 q10, q0, d5[1] @ {t1,t2,t5,t6}
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/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/gsoap/source/gsoap/samples/webserver/ |
H A D | webserver.c | 1004 const char *t0, *t1, *t2, *t3, *t4, *t5, *t6, *t7; local 1039 t6 = "<td align='center' bgcolor='green'>PASS</td>"; 1041 t6 = "<td align='center' bgcolor='yellow'>WAIT</td>"; 1045 t6 = "<td align='center' bgcolor='blue'>N/A</td>"; 1049 t6 = "<td align='center' bgcolor='blue'>N/A</td>"; 1102 </table>", t0, t1, t2, t3, t4, t5, t6, t7);
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/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/gsoap/source_build_platform/gsoap/samples/webserver/ |
H A D | webserver.c | 1004 const char *t0, *t1, *t2, *t3, *t4, *t5, *t6, *t7; local 1039 t6 = "<td align='center' bgcolor='green'>PASS</td>"; 1041 t6 = "<td align='center' bgcolor='yellow'>WAIT</td>"; 1045 t6 = "<td align='center' bgcolor='blue'>N/A</td>"; 1049 t6 = "<td align='center' bgcolor='blue'>N/A</td>"; 1102 </table>", t0, t1, t2, t3, t4, t5, t6, t7);
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/mips/kernel/ |
H A D | scall32-o32.S | 152 lw t6, 20(t0) # argument #6 from usp 163 sw t6, 20(sp) # argument #6 to ksp 168 sw t6, 20(sp) # argument #6 to ksp 222 lw t6, 28(sp) 225 sw t6, 24(sp)
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/mips/lib/ |
H A D | csum_partial.S | 33 #define t6 $14 define 445 EXC( LOAD t6, UNIT(6)(src), .Ll_exc_copy) 461 EXC( STORE t6, UNIT(6)(dst), .Ls_exc) 462 ADDC(sum, t6)
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H A D | memcpy-inatomic.S | 134 #define t6 $14 define
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/include/linux/ |
H A D | syscalls.h | 83 #define __SC_DECL6(t6, a6, ...) t6 a6, __SC_DECL5(__VA_ARGS__) 90 #define __SC_LONG6(t6, a6, ...) long a6, __SC_LONG5(__VA_ARGS__) 97 #define __SC_CAST6(t6, a6, ...) (t6) a6, __SC_CAST5(__VA_ARGS__) 105 #define __SC_TEST6(t6, a6, ...) __SC_TEST(t6); __SC_TEST5(__VA_ARGS__)
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