/netbsd-current/external/apache2/llvm/dist/clang/lib/Analysis/ |
H A D | ProgramPoint.cpp | 73 Out << RS->getID(Context) << ", \"stmt\": "; 191 << "\", \"stmt_id\": " << S->getID(Context)
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86InstructionSelector.cpp | 171 if (RB.getID() == X86::GPRRegBankID) { 181 if (RB.getID() == X86::VECRRegBankID) { 245 if (DstSize > SrcSize && SrcRegBank.getID() == X86::GPRRegBankID && 246 DstRegBank.getID() == X86::GPRRegBankID) { 281 if (SrcRegBank.getID() == X86::GPRRegBankID && 282 DstRegBank.getID() == X86::GPRRegBankID && SrcSize > DstSize && 405 if (X86::GPRRegBankID == RB.getID()) 408 if (X86::GPRRegBankID == RB.getID()) 411 if (X86::GPRRegBankID == RB.getID()) 413 if (X86::VECRRegBankID == RB.getID()) [all...] |
H A D | X86TileConfig.cpp | 121 if (MRI.getRegClass(VirtReg)->getID() != X86::TILERegClassID)
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64RegisterBankInfo.cpp | 237 switch (RC.getID()) { 390 assert((OpdMapper.getInstrMapping().getID() >= 1 && 391 OpdMapper.getInstrMapping().getID() <= 4) && 634 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size), 653 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size),
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H A D | AArch64InstructionSelector.cpp | 486 if (RB.getID() == AArch64::GPRRegBankID) { 498 if (RB.getID() == AArch64::FPRRegBankID) { 518 unsigned RegBankID = RB.getID(); 581 switch (RB.getID()) { 793 assert((DstSize <= 64 || DstBank.getID() == AArch64::FPRRegBankID) && 1046 assert(RBI.getRegBank(False, MRI, TRI)->getID() == 1047 RBI.getRegBank(True, MRI, TRI)->getID() && 1056 if (RBI.getRegBank(True, MRI, TRI)->getID() != AArch64::GPRRegBankID) { 1443 assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() == 1924 if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() [all...] |
/netbsd-current/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/ |
H A D | ExplodedGraph.cpp | 287 getFirstPred()->getState()->getID() == getState()->getID() && 498 N->getID(), N->isSink());
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUInstructionSelector.cpp | 88 return RB->getID() == AMDGPU::VCCRegBankID; 284 if (DstRB->getID() != AMDGPU::SGPRRegBankID && 285 DstRB->getID() != AMDGPU::VCCRegBankID) 288 bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID && 311 const bool IsSALU = DstRB->getID() == AMDGPU::SGPRRegBankID; 600 if (DstBank->getID() != AMDGPU::SGPRRegBankID) 1138 const bool IsVALU = DstBank->getID() == AMDGPU::VGPRRegBankID; 1160 unsigned Mov = DstRB->getID() == AMDGPU::SGPRRegBankID ? 1328 if (OffsetRB->getID() != AMDGPU::SGPRRegBankID) 1851 const bool IsVALU = DstRB->getID() [all...] |
H A D | AMDGPURegisterBankInfo.cpp | 215 unsigned BankID = Bank.getID(); 223 if (Dst.getID() == AMDGPU::SGPRRegBankID && 224 (isVectorRegisterBank(Src) || Src.getID() == AMDGPU::VCCRegBankID)) { 236 (Dst.getID() == AMDGPU::SGPRRegBankID) && 238 Src.getID() == AMDGPU::SGPRRegBankID || 239 Src.getID() == AMDGPU::VCCRegBankID)) 243 if (Dst.getID() == AMDGPU::AGPRRegBankID && 244 Src.getID() == AMDGPU::AGPRRegBankID) 1050 if (OpBank->getID() != AMDGPU::SGPRRegBankID) 2486 SrcBank->getID() [all...] |
H A D | AMDGPURegBankCombiner.cpp | 69 return RBI.getRegBank(Reg, MRI, TRI)->getID() == AMDGPU::VGPRRegBankID;
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | TargetPassConfig.h | 68 AnalysisID getID() const { function in class:llvm::IdentifyingPassPtr
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | RegisterClassInfo.cpp | 94 RCInfo &RCI = RegClass[RC->getID()];
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H A D | TargetPassConfig.cpp | 335 Pass *NP = Pass::createPass(InsertedPassID.getID()); 607 TargetPassID != InsertedPassID.getID()) || 681 FinalPtr.getID() != ID; 746 P = Pass::createPass(FinalPtr.getID());
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/netbsd-current/external/apache2/llvm/dist/clang/tools/diagtool/ |
H A D | TreeView.cpp | 117 NonRootGroupIDs.insert((unsigned)SI.getID());
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyPeephole.cpp | 98 switch (RegClass->getID()) {
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/netbsd-current/external/apache2/llvm/dist/clang/lib/Frontend/ |
H A D | LogDiagnosticPrinter.cpp | 129 DE.DiagnosticID = Info.getID();
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
H A D | Statepoint.h | 89 uint64_t getID() const { function in class:llvm::StatepointFlags::GCStatepointInst
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/netbsd-current/external/apache2/llvm/dist/clang/lib/ASTMatchers/ |
H A D | ASTMatchFinder.cpp | 421 Timer.setBucket(&TimeByBucket[MC->getID()]); 431 Timer.setBucket(&TimeByBucket[MC->getID()]); 587 Key.MatcherID = Matcher.getID(); 814 Timer.setBucket(&TimeByBucket[MP.second->getID()]); 838 Timer.setBucket(&TimeByBucket[MP.second->getID()]); 954 Keys.back().MatcherID = Matcher.getID(); 1450 StringRef MatchFinder::MatchCallback::getID() const { return "<unknown>"; } function in class:clang::ast_matchers::MatchFinder::MatchCallback
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGRRList.cpp | 326 RegClass = RC->getID(); 335 RegClass = RC->getID(); 343 RegClass = RC->getID(); 348 RegClass = TLI->getRepRegClassFor(VT)->getID(); 1768 RegLimit[RC->getID()] = tri->getRegPressureLimit(RC, MF); 2077 unsigned Id = RC->getID(); 2122 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); 2153 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); 2168 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); 2276 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/ |
H A D | GICombinerEmitter.cpp | 199 RuleID getID() const { return ID; } function in class:__anon3303::CombineRule 331 format("__anon%" PRIu64 "_%u", Rule.getID(), Rule.allocUID()))); 340 format("__anonpred%" PRIu64 "_%u", Rule.getID(), Rule.allocUID()))); 634 SS << "return " << EnumeratedRule.getID() << ";\n"; 742 << Indent << "if (!RuleConfig->isRuleDisabled(" << Rule->getID()
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H A D | OptParserEmitter.cpp | 411 unsigned AID = (*A)->getID(); 412 unsigned BID = (*B)->getID();
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Option/ |
H A D | OptTable.cpp | 96 OptSpecifier::OptSpecifier(const Option *Opt) : ID(Opt->getID()) {} 163 unsigned id = Opt.getID(); 655 HelpText = getOptionHelpText(Alias.getID());
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/netbsd-current/external/apache2/llvm/dist/clang/lib/ARCMigrate/ |
H A D | ARCMT.cpp | 39 llvm::is_contained(IDs, I->getID())) && 68 llvm::find(IDs, I->getID()) != IDs.end()) && 135 if (DiagnosticIDs::isARCDiagnostic(Info.getID()) ||
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMRegisterBankInfo.cpp | 52 PM.RegBank->getID() == RegBankID; 182 switch (RC.getID()) { 479 (Mapping.RegBank->getID() != ARM::FPRRegBankID ||
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonMachineScheduler.h | 192 return Available.getID() == ConvergingVLIWScheduler::TopQID;
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.cpp | 73 assert(Idx == RegBank.getID() && 269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); 639 OS << "ID: " << getID() << " Cost: " << getCost() << " Mapping: "; 779 OS << "Mapping ID: " << getInstrMapping().getID() << ' ';
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