/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 289 const MCInstrDesc &Desc = MI.getDesc();
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | TargetInstrInfo.h | 127 (MI.getDesc().isRematerializable() && 913 assert(MI.getDesc().isSelect() && "MI must be a select instruction"); 1472 return MI.getDesc().isPredicable();
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H A D | MachineInstr.h | 475 const MCInstrDesc &getDesc() const { return *MCID; } function in class:llvm::MachineInstr 770 return getDesc().getFlags() & (1ULL << MCFlag);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86AvoidStoreForwardingBlocks.cpp | 292 const MCInstrDesc &Descl = MI->getDesc(); 352 if (MI.getDesc().isCall()) 376 if (PBInst->getDesc().isCall())
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H A D | X86FloatingPoint.cpp | 420 uint64_t Flags = MI.getDesc().TSFlags; 1121 unsigned NumOps = MI.getDesc().getNumOperands(); 1182 unsigned NumOps = MI.getDesc().getNumOperands(); 1293 unsigned NumOperands = MI.getDesc().getNumOperands(); 1392 unsigned NumOperands = MI.getDesc().getNumOperands();
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H A D | X86SpeculativeLoadHardening.cpp | 1326 const MCInstrDesc &Desc = MI.getDesc(); 1369 !isEFLAGSDefLive(MI) && MI.getDesc().getNumDefs() == 1 && 1405 const MCInstrDesc &Desc = MI.getDesc(); 1807 const MCInstrDesc &Desc = UseMI.getDesc(); 1838 if (UseMI.getDesc().getNumDefs() > 1)
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H A D | X86MCInstLower.cpp | 961 uint64_t TSFlags = MI->getDesc().TSFlags; 962 if (MI->getDesc().isCommutable() && 2015 if (X86II::isKMasked(MI->getDesc().TSFlags)) { 2018 if (X86II::isKMergeMasked(MI->getDesc().TSFlags)) { 2030 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]); 2093 if (X86II::isKMasked(MI->getDesc().TSFlags)) { 2096 if (X86II::isKMergeMasked(MI->getDesc().TSFlags)) { 2108 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]); 2137 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]); 2152 unsigned Width = getRegisterWidth(MI->getDesc() [all...] |
H A D | X86InstrInfo.h | 558 return MI.getDesc().TSFlags & X86II::LOCK;
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H A D | X86CallFrameOptimization.cpp | 563 unsigned NumOps = DefMov->getDesc().getNumOperands();
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H A D | X86CallLowering.cpp | 360 *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsBranchExpansion.cpp | 226 for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; ++I) { 342 for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; ++I) { 721 assert(I.Br->getDesc().getNumOperands() == 1);
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H A D | MipsDelaySlotFiller.cpp | 349 update(MI, 0, MI.getDesc().getNumOperands()); 359 update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.cpp | 311 const MCInstrDesc &MCID = MI.getDesc(); 894 const MCInstrDesc &MCID = MI->getDesc(); 1193 const MCInstrDesc &MCID = MI.getDesc(); 1518 return MI.getDesc().getSize(); 1841 unsigned Flags = Itr->getDesc().TSFlags; 1861 unsigned Flags = CCUsers[Idx]->getDesc().TSFlags; 1943 const MCInstrDesc &MCID = MI.getDesc();
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H A D | SystemZShortenInst.cpp | 68 if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 &&
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | MachineLICM.cpp | 830 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) { 1071 unsigned NumDefs = MI.getDesc().getNumDefs(); 1166 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
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H A D | TwoAddressInstructionPass.cpp | 1070 unsigned OpsNum = MI->getDesc().getNumOperands(); 1071 unsigned OtherOpIdx = MI->getDesc().getNumDefs(); 1111 OpsNum = MI->getDesc().getNumOperands(); 1318 const MCInstrDesc &MCID = MI->getDesc();
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H A D | LiveRangeEdit.cpp | 294 MI->getDesc().getNumDefs() == 1) {
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
H A D | CodeMoverUtils.cpp | 271 << Stat.getDesc());
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyMCInstLower.cpp | 238 const MCInstrDesc &Desc = MI->getDesc();
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCInstrInfo.h | 118 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerInfo.cpp | 490 const MCOperandInfo *OpInfo = MI.getDesc().OpInfo; 492 for (unsigned i = 0; i < MI.getDesc().getNumOperands(); ++i) {
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H A D | Utils.cpp | 167 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI); 172 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/Object/ |
H A D | ELFTypes.h | 639 ArrayRef<uint8_t> getDesc() const { 650 ArrayRef<uint8_t> Desc = getDesc();
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | Thumb2InstrInfo.cpp | 523 const MCInstrDesc &Desc = MI.getDesc(); 762 const MCInstrDesc &MCID = MI.getDesc();
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
H A D | LanaiInstrInfo.cpp | 514 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg); 517 const MCInstrDesc &DefDesc = DefMI->getDesc();
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