Searched refs:getDesc (Results 76 - 100 of 156) sorted by relevance

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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp289 const MCInstrDesc &Desc = MI.getDesc();
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h127 (MI.getDesc().isRematerializable() &&
913 assert(MI.getDesc().isSelect() && "MI must be a select instruction");
1472 return MI.getDesc().isPredicable();
H A DMachineInstr.h475 const MCInstrDesc &getDesc() const { return *MCID; } function in class:llvm::MachineInstr
770 return getDesc().getFlags() & (1ULL << MCFlag);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp292 const MCInstrDesc &Descl = MI->getDesc();
352 if (MI.getDesc().isCall())
376 if (PBInst->getDesc().isCall())
H A DX86FloatingPoint.cpp420 uint64_t Flags = MI.getDesc().TSFlags;
1121 unsigned NumOps = MI.getDesc().getNumOperands();
1182 unsigned NumOps = MI.getDesc().getNumOperands();
1293 unsigned NumOperands = MI.getDesc().getNumOperands();
1392 unsigned NumOperands = MI.getDesc().getNumOperands();
H A DX86SpeculativeLoadHardening.cpp1326 const MCInstrDesc &Desc = MI.getDesc();
1369 !isEFLAGSDefLive(MI) && MI.getDesc().getNumDefs() == 1 &&
1405 const MCInstrDesc &Desc = MI.getDesc();
1807 const MCInstrDesc &Desc = UseMI.getDesc();
1838 if (UseMI.getDesc().getNumDefs() > 1)
H A DX86MCInstLower.cpp961 uint64_t TSFlags = MI->getDesc().TSFlags;
962 if (MI->getDesc().isCommutable() &&
2015 if (X86II::isKMasked(MI->getDesc().TSFlags)) {
2018 if (X86II::isKMergeMasked(MI->getDesc().TSFlags)) {
2030 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2093 if (X86II::isKMasked(MI->getDesc().TSFlags)) {
2096 if (X86II::isKMergeMasked(MI->getDesc().TSFlags)) {
2108 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2137 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2152 unsigned Width = getRegisterWidth(MI->getDesc()
[all...]
H A DX86InstrInfo.h558 return MI.getDesc().TSFlags & X86II::LOCK;
H A DX86CallFrameOptimization.cpp563 unsigned NumOps = DefMov->getDesc().getNumOperands();
H A DX86CallLowering.cpp360 *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsBranchExpansion.cpp226 for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; ++I) {
342 for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; ++I) {
721 assert(I.Br->getDesc().getNumOperands() == 1);
H A DMipsDelaySlotFiller.cpp349 update(MI, 0, MI.getDesc().getNumOperands());
359 update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp311 const MCInstrDesc &MCID = MI.getDesc();
894 const MCInstrDesc &MCID = MI->getDesc();
1193 const MCInstrDesc &MCID = MI.getDesc();
1518 return MI.getDesc().getSize();
1841 unsigned Flags = Itr->getDesc().TSFlags;
1861 unsigned Flags = CCUsers[Idx]->getDesc().TSFlags;
1943 const MCInstrDesc &MCID = MI.getDesc();
H A DSystemZShortenInst.cpp68 if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 &&
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineLICM.cpp830 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
1071 unsigned NumDefs = MI.getDesc().getNumDefs();
1166 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
H A DTwoAddressInstructionPass.cpp1070 unsigned OpsNum = MI->getDesc().getNumOperands();
1071 unsigned OtherOpIdx = MI->getDesc().getNumDefs();
1111 OpsNum = MI->getDesc().getNumOperands();
1318 const MCInstrDesc &MCID = MI->getDesc();
H A DLiveRangeEdit.cpp294 MI->getDesc().getNumDefs() == 1) {
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
H A DCodeMoverUtils.cpp271 << Stat.getDesc());
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMCInstLower.cpp238 const MCInstrDesc &Desc = MI->getDesc();
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h118 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerInfo.cpp490 const MCOperandInfo *OpInfo = MI.getDesc().OpInfo;
492 for (unsigned i = 0; i < MI.getDesc().getNumOperands(); ++i) {
H A DUtils.cpp167 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI);
172 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/Object/
H A DELFTypes.h639 ArrayRef<uint8_t> getDesc() const {
650 ArrayRef<uint8_t> Desc = getDesc();
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp523 const MCInstrDesc &Desc = MI.getDesc();
762 const MCInstrDesc &MCID = MI.getDesc();
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp514 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
517 const MCInstrDesc &DefDesc = DefMI->getDesc();

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