Searched refs:MULHU (Results 26 - 40 of 40) sorted by relevance
12
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 519 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1074 setOperationAction(ISD::MULHU, VT, Legal);
1077 setOperationAction(ISD::MULHU, VT, Expand);
1138 setOperationAction(ISD::MULHU, VT, Custom);
1293 setOperationAction(ISD::MULHU, MVT::v1i64, Custom);
1294 setOperationAction(ISD::MULHU, MVT::v2i64, Custom);
1493 setOperationAction(ISD::MULHU, VT, Custom);
3010 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
4625 case ISD::MULHU:
|
| H A D | AArch64FastISel.cpp | 3720 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, RHSReg);
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 338 setOperationAction(ISD::MULHU, VT, Expand);
837 setOperationAction(ISD::MULHU, VT, Expand);
937 setOperationAction(ISD::MULHU, MVT::v4i32, Custom);
939 setOperationAction(ISD::MULHU, MVT::v16i8, Custom);
941 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
1341 setOperationAction(ISD::MULHU, MVT::v8i32, Custom);
1343 setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom);
1345 setOperationAction(ISD::MULHU, MVT::v32i8, Custom);
1640 setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
1643 setOperationAction(ISD::MULHU, MV
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2425 case ISD::MULHU:
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 86 ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) {
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 170 // VE has no MULHU/S or U/SMUL_LOHI operations.
172 setOperationAction(ISD::MULHU, IntVT, Expand);
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 128 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU,
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1013 case ISD::MULHU:
3011 case ISD::MULHU:
|
| H A D | DAGCombiner.cpp | 1636 case ISD::MULHU: return visitMULHU(N);
4525 if (!TLI.isOperationLegalOrCustom(ISD::MULHU, VT) && VT.isSimple() &&
4625 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
8499 unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU;
|
| H A D | SelectionDAG.cpp | 3016 case ISD::MULHU: {
5564 case ISD::MULHU:
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 207 setOperationAction(ISD::MULHU, XLenVT, Expand);
701 setOperationAction(ISD::MULHU, VT, Custom);
2347 case ISD::MULHU:
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 811 setOperationAction(ISD::MULHU, VT, Expand);
903 setOperationAction(ISD::MULHU, MVT::v2i64, Legal);
905 setOperationAction(ISD::MULHU, MVT::v4i32, Legal);
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 774 setOperationAction(ISD::MULHU, VT, Expand);
1118 setOperationAction(ISD::MULHU, MVT::i32, Expand);
14512 case ISD::MULHU:
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 5156 SDValue Top = DAG.getNode(isSigned ? ISD::MULHS : ISD::MULHU,
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 210 setOperationAction(ISD::MULHU, VT, Expand);
|
Completed in 895 milliseconds
12