/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===// 1232 SelectionDAG &DAG) const { 1239 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op), 1246 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op), 1253 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), 1260 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), 1267 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op), 1272 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 1318 static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL, argument 1324 Value = DAG 1347 convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL, CCValAssign &VA, SDValue Value) argument 1371 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1541 SelectionDAG &DAG = CLI.DAG; local 1993 emitIntrinsicWithCCAndChain(SelectionDAG &DAG, SDValue Op, unsigned Opcode) argument 2013 emitIntrinsicWithCC(SelectionDAG &DAG, SDValue Op, unsigned Opcode) argument 2056 adjustZeroCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument 2076 adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument 2232 adjustForSubtraction(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument 2302 adjustICmpTruncate(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument 2434 adjustForTestUnderMask(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument 2525 adjustForRedundantAnd(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument 2543 getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode, SDValue Call, unsigned CCValid, uint64_t CC, ISD::CondCode Cond) argument 3894 lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG, unsigned Opcode) const argument 4150 getCCResult(SelectionDAG &DAG, SDValue CCReg) argument 4471 getPermuteNode(SelectionDAG &DAG, const SDLoc &DL, const Permute &P, SDValue Op0, SDValue Op1) argument 4517 getGeneralPermuteNode(SelectionDAG &DAG, const SDLoc &DL, SDValue *Ops, const SmallVectorImpl<int> &Bytes) argument 4688 getNode(SelectionDAG &DAG, const SDLoc &DL) argument 5728 SelectionDAG &DAG = DCI.DAG; local 5867 SelectionDAG &DAG = DCI.DAG; local 5896 SelectionDAG &DAG = DCI.DAG; local 5917 SelectionDAG &DAG = DCI.DAG; local 5944 SelectionDAG &DAG = DCI.DAG; local 5978 SelectionDAG &DAG = DCI.DAG; local 6043 SelectionDAG &DAG = DCI.DAG; local 6104 SelectionDAG &DAG = DCI.DAG; local 6143 SelectionDAG &DAG = DCI.DAG; local 6184 SelectionDAG &DAG = DCI.DAG; local 6218 SelectionDAG &DAG = DCI.DAG; local 6284 SelectionDAG &DAG = DCI.DAG; local 6343 SelectionDAG &DAG = DCI.DAG; local 6365 SelectionDAG &DAG = DCI.DAG; local 6562 SelectionDAG &DAG = DCI.DAG; local 6586 SelectionDAG &DAG = DCI.DAG; local 6651 SelectionDAG &DAG = DCI.DAG; local 6668 SelectionDAG &DAG = DCI.DAG; local 6834 computeKnownBitsBinOp(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth, unsigned OpNo) argument 6848 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument 6942 computeNumSignBitsBinOp(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth, unsigned OpNo) argument 6966 ComputeNumSignBitsForTargetNode( SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | StatepointLowering.cpp | 80 Ops.push_back(Builder.DAG.getTargetConstant(StackMaps::ConstantOp, L, 82 Ops.push_back(Builder.DAG.getTargetConstant(Value, L, MVT::i64)); 109 MachineFrameInfo &MFI = Builder.DAG.getMachineFunction().getFrameInfo(); 133 return Builder.DAG.getFrameIndex(FI, ValueType); 140 SDValue SpillSlot = Builder.DAG.CreateStackTemporary(ValueType); 305 Builder.DAG.getTargetFrameIndex(*Index, Builder.getFrameIndexTy()); 324 // We are expecting DAG to have the following form: 378 Loc = Builder.DAG.getTargetFrameIndex(Index, Builder.getFrameIndexTy()); 385 MachineFrameInfo &MFI = Builder.DAG.getMachineFunction().getFrameInfo(); 394 auto &MF = Builder.DAG [all...] |
H A D | SelectionDAGAddressAnalysis.cpp | 1 //==- llvm/CodeGen/SelectionDAGAddressAnalysis.cpp - DAG Address Analysis --==// 24 const SelectionDAG &DAG, 64 const MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 90 const SelectionDAG &DAG, bool &IsAlias) { 92 BaseIndexOffset BasePtr0 = match(Op0, DAG); 93 BaseIndexOffset BasePtr1 = match(Op1, DAG); 99 BasePtr0.equalBaseIndex(BasePtr1, DAG, PtrDiff)) { 129 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 157 bool BaseIndexOffset::contains(const SelectionDAG &DAG, int64_t BitSize, argument 161 if (!equalBaseIndex(Other, DAG, Offse 23 equalBaseIndex(const BaseIndexOffset &Other, const SelectionDAG &DAG, int64_t &Off) const argument 86 computeAliasing(const SDNode *Op0, const Optional<int64_t> NumBytes0, const SDNode *Op1, const Optional<int64_t> NumBytes1, const SelectionDAG &DAG, bool &IsAlias) argument 178 matchLSNode(const LSBaseSDNode *N, const SelectionDAG &DAG) argument 281 match(const SDNode *N, const SelectionDAG &DAG) argument [all...] |
H A D | ScheduleDAGSDNodes.cpp | 50 : ScheduleDAG(mf), BB(nullptr), DAG(nullptr), 57 DAG = dag; 59 // Clear the scheduler's SUnit DAG. 80 const TargetLowering &TLI = DAG->getTargetLoweringInfo(); 140 static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef<EVT> VTs, argument 146 SDVTList VTList = DAG->getVTList(VTs); 154 DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops); 158 DAG->setNodeMemRefs(MN, MMOs); 161 static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) { argument 179 CloneNodeWithValues(N, DAG, VT 186 RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCMachineScheduler.cpp | 66 if (DAG->isTrackingPressure() && 68 RegExcess, TRI, DAG->MF)) 72 if (DAG->isTrackingPressure() && 74 TryCand, Cand, RegCritical, TRI, DAG->MF)) 102 // the scheduler pass by combining the loads during DAG postprocessing. 104 Cand.AtTop ? DAG->getNextClusterSucc() : DAG->getNextClusterPred(); 106 TryCand.AtTop ? DAG->getNextClusterSucc() : DAG->getNextClusterPred(); 119 if (DAG [all...] |
H A D | PPCHazardRecognizers.cpp | 29 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); 55 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 65 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); 147 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 161 DAG->MF.getSubtarget<PPCSubtarget>().getCPUDirective(); 175 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 182 LLVM_DEBUG(DAG->dumpNode(*SU)); 221 DAG->MF.getSubtarget<PPCSubtarget>().getCPUDirective(); 262 PPCHazardRecognizer970::PPCHazardRecognizer970(const ScheduleDAG &DAG) argument [all...] |
H A D | PPCTargetMachine.cpp | 280 ScheduleDAGMILive *DAG = local 284 // add DAG Mutations here. 285 DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI)); 287 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); 289 DAG->addMutation(createPowerPCMacroFusionDAGMutation()); 291 return DAG; 297 ScheduleDAGMI *DAG = local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.h | 1 //===-- BPFISelLowering.h - BPF DAG Lowering Interface ----------*- C++ -*-===// 10 // selection DAG. 40 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 42 // This method returns the name of a target specific DAG node. 75 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 76 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 77 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 83 const SDLoc &DL, SelectionDAG &DAG, 97 const SDLoc &DL, SelectionDAG &DAG, 103 SelectionDAG &DAG) cons [all...] |
H A D | BPFSelectionDAGInfo.h | 22 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.h | 1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===// 10 // selection DAG. 444 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 446 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 486 const SDLoc &dl, SelectionDAG &DAG, 500 SelectionDAG &DAG) const override; 504 SelectionDAG &DAG) const override; 532 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 556 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const; 558 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) cons [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
H A D | LanaiSelectionDAGInfo.h | 25 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonSelectionDAGInfo.h | 24 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
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H A D | HexagonSubtarget.cpp | 198 void HexagonSubtarget::UsrOverflowMutation::apply(ScheduleDAGInstrs *DAG) { argument 199 for (SUnit &SU : DAG->SUnits) { 211 void HexagonSubtarget::HVXMemLatencyMutation::apply(ScheduleDAGInstrs *DAG) { argument 212 for (SUnit &SU : DAG->SUnits) { 217 auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII); 263 ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs); local 270 auto &TRI = *DAG->MF.getSubtarget().getRegisterInfo(); 271 auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo(); 275 for (unsigned su = 0, e = DAG->SUnits.size(); su != e; ++su) { 277 if (DAG 332 apply(ScheduleDAGInstrs *DAG) argument [all...] |
H A D | HexagonMachineScheduler.cpp | 190 /// only includes instructions that have DAG nodes, not scheduling boundaries. 201 // Postprocess the DAG to add platform-specific artificial dependencies. 207 // Initialize the strategy before modifying the DAG. 236 // Notify the scheduling strategy after updating the DAG. 254 DAG = static_cast<VLIWMachineScheduler*>(dag); 255 SchedModel = DAG->getSchedModel(); 257 Top.init(DAG, SchedModel); 258 Bot.init(DAG, SchedModel); 262 const InstrItineraryData *Itin = DAG->getSchedModel()->getInstrItineraries(); 263 const TargetSubtargetInfo &STI = DAG [all...] |
H A D | HexagonMachineScheduler.h | 134 VLIWMachineScheduler *DAG = nullptr; member in struct:llvm::ConvergingVLIWScheduler::VLIWSchedBoundary 166 DAG = dag; 175 CriticalPathLength = DAG->getBBSize() / SchedModel->getIssueWidth(); 176 if (DAG->getBBSize() < 50) 185 for (auto &SU : DAG->SUnits) 217 VLIWMachineScheduler *DAG = nullptr; member in class:llvm::ConvergingVLIWScheduler
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineScheduler.h | 60 SIScheduleDAGMI *DAG; member in class:llvm::SIScheduleBlock 102 SIScheduleBlock(SIScheduleDAGMI *DAG, SIScheduleBlockCreator *BC, argument 104 DAG(DAG), BC(BC), TopRPTracker(TopPressure), ID(ID) {} 224 SIScheduleDAGMI *DAG; member in class:llvm::SIScheduleBlockCreator 248 SIScheduleBlockCreator(SIScheduleDAGMI *DAG); 320 SIScheduleDAGMI *DAG; member in class:llvm::SIScheduleBlockScheduler 347 SIScheduleBlockScheduler(SIScheduleDAGMI *DAG, 413 SIScheduleDAGMI *DAG; member in class:llvm::SIScheduler 417 SIScheduler(SIScheduleDAGMI *DAG) argument [all...] |
H A D | R600MachineScheduler.cpp | 24 DAG = static_cast<ScheduleDAGMILive*>(dag); 25 const R600Subtarget &ST = DAG->MF.getSubtarget<R600Subtarget>(); 26 TII = static_cast<const R600InstrInfo*>(DAG->TII); 27 TRI = static_cast<const R600RegisterInfo*>(DAG->TRI); 29 MRI = &DAG->MRI; 124 DAG->dumpNode(*SU); 127 for (unsigned i = 0; i < DAG->SUnits.size(); i++) { 128 const SUnit &S = DAG->SUnits[i]; 130 DAG->dumpNode(S); 185 LLVM_DEBUG(dbgs() << "Top Releasing "; DAG [all...] |
H A D | GCNSchedStrategy.cpp | 26 void GCNMaxOccupancySchedStrategy::initialize(ScheduleDAGMI *DAG) { argument 27 GenericScheduler::initialize(DAG); 31 MF = &DAG->MF; 47 SGPRCriticalLimit = SRI->getRegPressureSetLimit(DAG->MF, 49 VGPRCriticalLimit = SRI->getRegPressureSetLimit(DAG->MF, 77 // and can be retrieved by DAG->getPressureDif(SU). 162 TryCand.initResourceDelta(Zone.DAG, SchedModel); 196 pickNodeFromQueue(Bot, BotPolicy, DAG->getBotRPTracker(), BotCand); 204 pickNodeFromQueue(Bot, BotPolicy, DAG->getBotRPTracker(), TCand); 216 pickNodeFromQueue(Top, TopPolicy, DAG [all...] |
H A D | GCNMinRegStrategy.cpp | 75 const ScheduleDAG &DAG); 226 const ScheduleDAG &DAG) { 227 const auto &SUnits = DAG.SUnits; 238 releaseSuccessors(&DAG.EntrySU, StepNo); 253 LLVM_DEBUG(dbgs() << "Selected "; DAG.dumpNode(*SU)); 272 const ScheduleDAG &DAG) { 274 return S.schedule(TopRoots, DAG); 225 schedule(ArrayRef<const SUnit*> TopRoots, const ScheduleDAG &DAG) argument 271 makeMinRegSchedule(ArrayRef<const SUnit*> TopRoots, const ScheduleDAG &DAG) argument
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H A D | GCNILPSched.cpp | 51 const ScheduleDAG &DAG); 291 const ScheduleDAG &DAG) { 292 auto &SUnits = const_cast<ScheduleDAG&>(DAG).SUnits; 310 releasePredecessors(&DAG.ExitSU); 337 LLVM_DEBUG(dbgs() << "Selected "; DAG.dumpNode(*SU)); 358 const ScheduleDAG &DAG) { 360 return S.schedule(BotRoots, DAG); 290 schedule(ArrayRef<const SUnit*> BotRoots, const ScheduleDAG &DAG) argument 357 makeGCNILPScheduler(ArrayRef<const SUnit*> BotRoots, const ScheduleDAG &DAG) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | ScoreboardHazardRecognizer.h | 96 const ScheduleDAG *DAG; member in class:llvm::ScoreboardHazardRecognizer 109 const ScheduleDAG *DAG,
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H A D | TargetLowering.h | 105 Linearize // Linearize DAG, no scheduling 476 virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const { 542 const SelectionDAG &DAG, 558 return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT, 565 const SelectionDAG &DAG, 568 return isLoadBitCastBeneficial(StoreVT, BitcastVT, DAG, MMO); 589 const SelectionDAG &DAG) const { 741 SelectionDAG &DAG) const { 882 virtual bool shouldExpandShift(SelectionDAG &DAG, SDNod argument 541 isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const argument 564 isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const argument 2668 isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const argument 2714 isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const argument 3264 SelectionDAG &DAG; member in struct:llvm::TargetLoweringBase::TargetLowering::TargetLoweringOpt 3504 SelectionDAG &DAG; member in struct:llvm::TargetLoweringBase::TargetLowering::DAGCombinerInfo 3641 getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth = 0) const argument 3657 getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth = 0) const argument 3670 splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const argument 3679 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const argument 3726 SelectionDAG &DAG; member in struct:llvm::TargetLoweringBase::TargetLowering::CallLoweringInfo 3734 CallLoweringInfo(SelectionDAG &DAG) argument 4280 getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const argument 4296 getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const argument 4587 emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | ScoreboardHazardRecognizer.cpp | 34 DAG(SchedDAG) { 123 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 160 LLVM_DEBUG(DAG->dumpNode(*SU)); 178 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 180 if (DAG->TII->isZeroCost(MCID->Opcode))
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H A D | MachineScheduler.cpp | 142 // DAG subtrees must have at least this many nodes. 367 /// consistent with the DAG builder, which traverses the interior of the 370 /// This design avoids exposing scheduling boundaries to the DAG builder, 371 /// simplifying the DAG builder's support for "special" target instructions. 453 /// handle calls, the DAG builder needs to be modified to create register 549 // points to the scheduling boundary at the bottom of the region. The DAG 770 // Build the DAG. 782 // Initialize the strategy before modifying the DAG. 786 // Initialize ready queues now that the DAG and priority data are finalized. 819 // Notify the scheduling strategy before updating the DAG 1593 clusterNeighboringMemOps( ArrayRef<MemOpInfo> MemOpRecords, bool FastCluster, ScheduleDAGInstrs *DAG) argument 1708 groupMemOps( ArrayRef<MemOpInfo> MemOps, ScheduleDAGInstrs *DAG, DenseMap<unsigned, SmallVector<MemOpInfo, 32>> &Groups) argument 1739 apply(ScheduleDAGInstrs *DAG) argument 1820 constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG) argument 1945 ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs); local 2020 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) argument 2623 initResourceDelta(const ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) argument 3486 ScheduleDAGMILive *DAG = local 3684 ScheduleDAGMILive *DAG = nullptr; member in class:__anon1826::ILPScheduler 3899 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G); local 3914 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G); local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetMachine.cpp | 398 ScheduleDAGMILive *DAG = createGenericSchedLive(C); variable 399 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); 400 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); 402 DAG->addMutation(createAArch64MacroFusionDAGMutation()); 403 return DAG; 412 ScheduleDAGMI *DAG variable [all...] |