/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 1 //===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===// 10 // selection DAG. 831 // In another words, find a way when "copysign" appears in DAG with vector 1928 static bool isS16(const SDValue &Op, SelectionDAG &DAG) { argument 1931 return DAG.ComputeNumSignBits(Op) == 17; 1934 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 1951 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. 2062 SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, argument 2064 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()), 2067 Val = DAG 2076 MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT, SDValue Val) const argument 2093 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn, SDValue ThisVal) const argument 2182 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, const SDLoc &dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument 2196 PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVectorImpl<SDValue> &MemOpChains, ISD::ArgFlagsTy Flags) const argument 2228 SelectionDAG &DAG = CLI.DAG; local 2780 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG, const bool isIndirect) const argument 2917 LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, const SDLoc &DL, SelectionDAG &DAG) argument 3214 LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) argument 3474 LowerToTLSExecModels(GlobalAddressSDNode *GA, SelectionDAG &DAG, TLSModel::Model model) const argument 3570 promoteToConstantPool(const ARMTargetLowering *TLI, const GlobalValue *GV, SelectionDAG &DAG, EVT PtrVT, const SDLoc &dl) argument 3834 LowerINTRINSIC_VOID( SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const argument 3877 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const argument 4015 LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 4052 LowerPREFETCH(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 4079 LowerVASTART(SDValue Op, SelectionDAG &DAG) argument 4093 GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, const SDLoc &dl) const argument 4138 StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, SDValue &Chain, const Value *OrigArg, unsigned InRegsParamRecordIdx, int ArgOffset, unsigned ArgSize) const argument 4192 VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, SDValue &Chain, unsigned ArgOffset, unsigned TotalArgRegsSaveSize, bool ForceMutable) const argument 4212 splitValueIntoRegisterParts( SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const argument 4230 joinRegisterPartsIntoValue( SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const argument 4248 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 4495 getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const argument 4636 getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl, bool Signaling) const argument 4676 getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const argument 4768 ConvertBooleanCarryToCarryFlag(SDValue BoolCarry, SelectionDAG &DAG) argument 4781 ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT, SelectionDAG &DAG) argument 4829 LowerSADDSUBSAT(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 5043 LowerSaturatingConditional(SDValue Op, SelectionDAG &DAG) argument 5342 bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) argument 5354 expandf64Toi32(SDValue Op, SelectionDAG &DAG, SDValue &RetVal1, SDValue &RetVal2) argument 5592 LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) argument 5662 LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) argument 5866 ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) argument 5891 CombineVMOVDRRCandidateWithVecOp(const SDNode *BC, SelectionDAG &DAG) argument 5939 ExpandBITCAST(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const argument 6003 getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) argument 6160 LowerCTTZ(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 6216 LowerCTPOP(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 6302 LowerShift(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 6345 Expand64BitShift(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 6427 LowerVSETCC(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 6607 LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) argument 6640 isVMOVModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, const SDLoc &dl, EVT &VT, EVT VectorVT, VMOVModImmType type) argument 6790 LowerConstantFP(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) const argument 7268 LowerBuildVectorOfFPTrunc(SDValue BV, SelectionDAG &DAG, const ARMSubtarget *ST) argument 7321 LowerBuildVectorOfFPExt(SDValue BV, SelectionDAG &DAG, const ARMSubtarget *ST) argument 7363 IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST, const SDLoc &dl) argument 7380 LowerBUILD_VECTOR_i1(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 7440 LowerBUILD_VECTORToVIDUP(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 7475 LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) const argument 8007 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) argument 8066 LowerVECTOR_SHUFFLEv8i8(SDValue Op, ArrayRef<int> ShuffleMask, SelectionDAG &DAG) argument 8087 LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op, SelectionDAG &DAG) argument 8117 PromoteMVEPredVector(SDLoc dl, SDValue Pred, EVT VT, SelectionDAG &DAG) argument 8152 LowerVECTOR_SHUFFLE_i1(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 8192 LowerVECTOR_SHUFFLEUsingMovs(SDValue Op, ArrayRef<int> ShuffleMask, SelectionDAG &DAG) argument 8278 LowerVECTOR_SHUFFLEUsingOneOff(SDValue Op, ArrayRef<int> ShuffleMask, SelectionDAG &DAG) argument 8329 LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 8537 LowerINSERT_VECTOR_ELT_i1(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 8600 LowerEXTRACT_VECTOR_ELT_i1(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 8618 LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 8639 LowerCONCAT_VECTORS_i1(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 8691 LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 8716 LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 8754 LowerTruncatei1(SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 8773 isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, bool isSigned) argument 8826 isSignExtended(SDNode *N, SelectionDAG &DAG) argument 8836 isZeroExtended(SDNode *N, SelectionDAG &DAG) argument 8865 AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode) argument 8887 SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) argument 8911 SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) argument 8962 isAddSubSExt(SDNode *N, SelectionDAG &DAG) argument 8973 isAddSubZExt(SDNode *N, SelectionDAG &DAG) argument 8984 LowerMUL(SDValue Op, SelectionDAG &DAG) argument 9059 LowerSDIV_v4i8(SDValue X, SDValue Y, const SDLoc &dl, SelectionDAG &DAG) argument 9090 LowerSDIV_v4i16(SDValue N0, SDValue N1, const SDLoc &dl, SelectionDAG &DAG) argument 9129 LowerSDIV(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 9165 LowerUDIV(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 9242 LowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) argument 9361 LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed, SDValue &Chain) const argument 9403 BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl<SDNode *> &Created) const argument 9441 LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const argument 9453 WinDBZCheckDenominator(SelectionDAG &DAG, SDNode *N, SDValue InChain) argument 9466 ExpandDIV_Windows( SDValue Op, SelectionDAG &DAG, bool Signed, SmallVectorImpl<SDValue> &Results) const argument 9488 LowerPredicateLoad(SDValue Op, SelectionDAG &DAG) argument 9544 LowerPredicateStore(SDValue Op, SelectionDAG &DAG) argument 9581 LowerSTORE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 9619 LowerMLOAD(SDValue Op, SelectionDAG &DAG) argument 9646 LowerVecReduce(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 9712 LowerVecReduceF(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) argument 9719 LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) argument 9729 ReplaceREADCYCLECOUNTER(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 9752 createGPRPairNode(SelectionDAG &DAG, SDValue V) argument 9770 ReplaceCMP_SWAP_64Results(SDNode *N, SmallVectorImpl<SDValue> & Results, SelectionDAG &DAG) argument 9954 ReplaceLongIntrinsic(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) argument 11777 isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG) argument 11854 SelectionDAG &DAG = DCI.DAG; local 12369 SelectionDAG &DAG = DCI.DAG; local 12385 PerformUMLALCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 12444 SelectionDAG &DAG = DCI.DAG; local 12579 PerformVQDMULHCombine(SDNode *N, SelectionDAG &DAG) argument 12694 SelectionDAG &DAG = DCI.DAG; local 13109 PerformMVEVMULLCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 13177 SelectionDAG &DAG = DCI.DAG; local 13302 SelectionDAG &DAG = DCI.DAG; local 13371 SelectionDAG &DAG = DCI.DAG; local 13452 SelectionDAG &DAG = DCI.DAG; local 13484 SelectionDAG &DAG = DCI.DAG; local 13665 SelectionDAG &DAG = DCI.DAG; local 13762 SelectionDAG &DAG = DCI.DAG; local 13952 SelectionDAG &DAG = DCI.DAG; local 14027 PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) argument 14144 SelectionDAG &DAG = DCI.DAG; local 14484 PerformSignExtendInregCombine(SDNode *N, SelectionDAG &DAG) argument 14501 FlattenVectorShuffle(ShuffleVectorSDNode *N, SelectionDAG &DAG) argument 14539 PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) argument 14599 SelectionDAG &DAG = DCI.DAG; local 14961 SelectionDAG &DAG = DCI.DAG; local 15085 SelectionDAG &DAG = DCI.DAG; local 15137 PerformTruncatingStoreCombine(StoreSDNode *St, SelectionDAG &DAG) argument 15222 PerformSplittingToNarrowingStores(StoreSDNode *St, SelectionDAG &DAG) argument 15331 PerformExtractFpToIntStores(StoreSDNode *St, SelectionDAG &DAG) argument 15392 SelectionDAG &DAG = DCI.DAG; local 15415 SelectionDAG &DAG = DCI.DAG; local 15451 PerformVCVTCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 15508 PerformVDIVCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 15558 PerformVECREDUCE_ADDCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 15842 PerformLongShiftCombine(SDNode *N, SelectionDAG &DAG) argument 15873 SelectionDAG &DAG = DCI.DAG; local 16101 SelectionDAG &DAG = DCI.DAG; local 16187 PerformSplittingToWideningLoad(SDNode *N, SelectionDAG &DAG) argument 16270 PerformExtendCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 16313 PerformFPExtendCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 16324 PerformMinMaxCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 16633 SelectionDAG &DAG = DCI.DAG; local 16914 SelectionDAG &DAG = DCI.DAG; local 17793 getARMIndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) argument 17852 getT2IndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) argument 17877 getMVEIndexedAddressParts(SDNode *Ptr, EVT VT, Align Alignment, bool isSEXTLoad, bool IsMasked, bool isLE, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) argument 18081 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument 19483 shouldExpandShift(SelectionDAG &DAG, SDNode *N) const argument [all...] |
H A D | ARMSelectionDAGInfo.h | 40 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, 48 EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, 55 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, 60 SDValue EmitSpecializedLibcall(SelectionDAG &DAG, const SDLoc &dl,
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===// 191 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) { argument 192 assert(VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 1628 // independent DAG combine optimize this node. 1630 New = TLO.DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0), 1631 TLO.DAG.getConstant(NewImm, DL, VT)); 1632 // Otherwise, create a machine node so that target independent DAG combine 1636 SDValue EncConst = TLO.DAG.getTargetConstant(Enc, DL, VT); 1638 TLO.DAG.getMachineNode(NewOpc, DL, VT, Op.getOperand(0), EncConst), 0); 1691 const APInt &DemandedElts, const SelectionDAG &DAG, unsigne 1689 computeKnownBitsForTargetNode( const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument 2398 emitStrictFPComparison(SDValue LHS, SDValue RHS, const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, bool IsSignaling) argument 2409 emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) argument 2515 emitConditionalComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue CCOp, AArch64CC::CondCode Predicate, AArch64CC::CondCode OutCC, const SDLoc &DL, SelectionDAG &DAG) argument 2625 emitConjunctionRec(SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp, AArch64CC::CondCode Predicate) argument 2737 emitConjunction(SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC) argument 2785 getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, const SDLoc &dl) argument 2917 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) argument 3114 LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) argument 3150 LowerXALUO(SDValue Op, SelectionDAG &DAG) argument 3181 LowerPREFETCH(SDValue Op, SelectionDAG &DAG) argument 3498 addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode) argument 3515 isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, bool isSigned) argument 3541 skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) argument 3566 isSignExtended(SDNode *N, SelectionDAG &DAG) argument 3572 isZeroExtended(SDNode *N, SelectionDAG &DAG) argument 3578 isAddSubSExt(SDNode *N, SelectionDAG &DAG) argument 3589 isAddSubZExt(SDNode *N, SelectionDAG &DAG) argument 3743 getPTrue(SelectionDAG &DAG, SDLoc DL, EVT VT, int Pattern) argument 3749 lowerConvertToSVBool(SDValue Op, SelectionDAG &DAG) argument 4181 selectGatherScatterAddrMode(SDValue &BasePtr, SDValue &Index, EVT MemVT, unsigned &Opcode, bool IsGather, SelectionDAG &DAG) argument 4335 LowerTruncateVectorStore(SDLoc DL, StoreSDNode *ST, EVT VT, EVT MemVT, SelectionDAG &DAG) argument 4808 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 5111 saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL, SDValue &Chain) const argument 5197 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn, SDValue ThisVal) const argument 5426 addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const argument 5470 SelectionDAG &DAG = CLI.DAG; local 6093 getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument 6100 getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument 6106 getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument 6113 getTargetNode(BlockAddressSDNode* N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument 6121 getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const argument 6134 getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const argument 6150 getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const argument 6164 getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const argument 7666 getEstimate(const AArch64Subtarget *ST, unsigned Opcode, SDValue Operand, SelectionDAG &DAG, int &ExtraSteps) argument 7689 getSqrtInputTest(SDValue Op, SelectionDAG &DAG, const DenormalMode &Mode) const argument 7704 getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &ExtraSteps, bool &UseOneConst, bool Reciprocal) const argument 7737 getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &ExtraSteps) const argument 8153 WidenVector(SDValue V64Reg, SelectionDAG &DAG) argument 8173 NarrowVector(SDValue V128Reg, SelectionDAG &DAG) argument 8740 tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) argument 8770 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) argument 8873 GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask, SelectionDAG &DAG) argument 8948 constructDup(SDValue V, int Lane, SDLoc dl, EVT VT, unsigned Opcode, SelectionDAG &DAG) argument 9293 tryAdvSIMDModImm64(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) argument 9314 tryAdvSIMDModImm32(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits, const SDValue *LHS = nullptr) argument 9362 tryAdvSIMDModImm16(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits, const SDValue *LHS = nullptr) argument 9402 tryAdvSIMDModImm321s(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) argument 9433 tryAdvSIMDModImm8(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) argument 9454 tryAdvSIMDModImmFP(unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits) argument 9524 tryLowerToSLI(SDNode *N, SelectionDAG &DAG) argument 9652 NormalizeBuildVector(SDValue Op, SelectionDAG &DAG) argument 9683 ConstantBuildVector(SDValue Op, SelectionDAG &DAG) argument 10413 EmitVectorComparison(SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, const SDLoc &dl, SelectionDAG &DAG) argument 10578 getReductionSDNode(unsigned Op, SDLoc DL, SDValue ScalarOp, SelectionDAG &DAG) argument 11585 LowerSVEStructLoad(unsigned Intrinsic, ArrayRef<SDValue> LoadOps, EVT VT, SelectionDAG &DAG, const SDLoc &DL) const argument 11877 foldVectorXorShiftIntoCmp(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument 11903 performVecReduceAddCombine(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *ST) argument 11948 performABSCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument 11987 performXorCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument 11997 BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl<SDNode *> &Created) const argument 12064 calculatePreExtendType(SDValue Extend, SelectionDAG &DAG) argument 12103 performCommonVectorExtendCombine(SDValue VectorShuffle, SelectionDAG &DAG) argument 12178 performMulVectorExtendCombine(SDNode *Mul, SelectionDAG &DAG) argument 12196 performMulCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument 12308 performVectorCompareAndMaskUnaryOpCombine(SDNode *N, SelectionDAG &DAG) argument 12354 performIntToFpCombine(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument 12395 performFpToIntCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument 12470 performFDivCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument 12563 SelectionDAG &DAG = DCI.DAG; local 12604 SelectionDAG &DAG = DCI.DAG; local 12694 SelectionDAG &DAG = DCI.DAG; local 12827 SelectionDAG &DAG = DCI.DAG; local 12875 SelectionDAG &DAG = DCI.DAG; local 12913 performVectorTruncateCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 12995 performExtractVectorEltCombine(SDNode *N, SelectionDAG &DAG) argument 13038 performConcatVectorsCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 13167 tryCombineFixedPointConvert(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 13229 tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) argument 13362 performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) argument 13409 performUADDVCombine(SDNode *N, SelectionDAG &DAG) argument 13446 performAddDotCombine(SDNode *N, SelectionDAG &DAG) argument 13479 performAddSubLongCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 13521 performAddSubCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 13540 tryCombineLongOpWithDup(unsigned IID, SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 13572 tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) argument 13643 tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) argument 13656 combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N, SelectionDAG &DAG) argument 13666 LowerSVEIntrinsicIndex(SDNode *N, SelectionDAG &DAG) argument 13684 LowerSVEIntrinsicDUP(SDNode *N, SelectionDAG &DAG) argument 13698 LowerSVEIntrinsicEXT(SDNode *N, SelectionDAG &DAG) argument 13724 tryConvertSVEWideCompare(SDNode *N, ISD::CondCode CC, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 13788 getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op, AArch64CC::CondCode Cond) argument 13812 combineSVEReductionInt(SDNode *N, unsigned Opc, SelectionDAG &DAG) argument 13831 combineSVEReductionFP(SDNode *N, unsigned Opc, SelectionDAG &DAG) argument 13848 combineSVEReductionOrderedFP(SDNode *N, unsigned Opc, SelectionDAG &DAG) argument 13896 convertMergedOpToPredOp(SDNode *N, unsigned Opc, SelectionDAG &DAG, bool UnpredOp = false) argument 13920 SelectionDAG &DAG = DCI.DAG; local 14144 performExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 14165 splitStoreSplat(SelectionDAG &DAG, StoreSDNode &St, SDValue SplatVal, unsigned NumVecElts) argument 14235 performLD1Combine(SDNode *N, SelectionDAG &DAG, unsigned Opc) argument 14261 performLDNT1Combine(SDNode *N, SelectionDAG &DAG) argument 14291 performLD1ReplicateCombine(SDNode *N, SelectionDAG &DAG) argument 14315 performST1Combine(SDNode *N, SelectionDAG &DAG) argument 14345 performSTNT1Combine(SDNode *N, SelectionDAG &DAG) argument 14381 replaceZeroVectorStore(SelectionDAG &DAG, StoreSDNode &St) argument 14448 replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode &St) argument 14501 splitStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument 14572 performUzpCombine(SDNode *N, SelectionDAG &DAG) argument 14597 performGLD1Combine(SDNode *N, SelectionDAG &DAG) argument 14786 performTBISimplification(SDValue Addr, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 14801 performSTORECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument 14817 performNEONPostLDSTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 15135 performCONDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, unsigned CCIndex, unsigned CmpIndex) argument 15209 performBRCONDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 15272 performCSELCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 15286 getTestBitOperand(SDValue Op, unsigned &Bit, bool &Invert, SelectionDAG &DAG) argument 15359 performTBZCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 15390 performVSelectCombine(SDNode *N, SelectionDAG &DAG) argument 15454 SelectionDAG &DAG = DCI.DAG; local 15526 performGlobalAddressCombine(SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget, const TargetMachine &TM) argument 15578 getScaledOffsetForBitWidth(SelectionDAG &DAG, SDValue Offset, SDLoc DL, unsigned BitWidth) argument 15624 performScatterStoreCombine(SDNode *N, SelectionDAG &DAG, unsigned Opcode, bool OnlyPackedOffsets = true) argument 15728 performGatherLoadCombine(SDNode *N, SelectionDAG &DAG, unsigned Opcode, bool OnlyPackedOffsets = true) argument 15830 performSignExtendInRegCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 15962 legalizeSVEGatherPrefetchOffsVec(SDNode *N, SelectionDAG &DAG) argument 15985 combineSVEPrefetchVecBaseImmOff(SDNode *N, SelectionDAG &DAG, unsigned ScalarSizeInBytes) argument 16075 SelectionDAG &DAG = DCI.DAG; local 16525 ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) argument 16543 ReplaceReductionResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG, unsigned InterOp, unsigned AcrossOp) argument 16557 splitInt128(SDValue N, SelectionDAG &DAG) argument 16601 createGPRPairNode(SelectionDAG &DAG, SDValue V) argument 16618 ReplaceCMP_SWAP_128Results(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument 17099 shouldExpandShift(SelectionDAG &DAG, SDNode *N) const argument 17233 getContainerForFixedLengthVector(SelectionDAG &DAG, EVT VT) argument 17258 getPredicateForFixedLengthVector(SelectionDAG &DAG, SDLoc &DL, EVT VT) argument 17326 getPredicateForScalableVector(SelectionDAG &DAG, SDLoc &DL, EVT VT) argument 17334 getPredicateForVector(SelectionDAG &DAG, SDLoc &DL, EVT VT) argument 17342 convertToScalableVector(SelectionDAG &DAG, EVT VT, SDValue V) argument 17353 convertFromScalableVector(SelectionDAG &DAG, EVT VT, SDValue V) argument 17383 convertFixedMaskToScalableVector(SDValue Mask, SelectionDAG &DAG) argument 17644 LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, unsigned NewOp, bool OverrideNEON) const argument [all...] |
H A D | AArch64SelectionDAGInfo.h | 22 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, 27 SDValue EmitTargetCodeForSetTag(SelectionDAG &DAG, const SDLoc &dl,
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 1 //===- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface -------------===// 409 SDValue MipsSETargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const { 411 return MipsTargetLowering::LowerOperation(Op, DAG); 419 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); 420 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), 450 SelectionDAG &DAG) const { 452 case ISD::LOAD: return lowerLOAD(Op, DAG); 453 case ISD::STORE: return lowerSTORE(Op, DAG); 454 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); 455 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); 482 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 597 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 717 shouldTransformMulToShiftsAddsSubs(APInt C, EVT VT, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument 793 genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG) argument 829 performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL, const MipsSubtarget &Subtarget) argument 845 performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument 870 performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 893 performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 939 performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 968 performSETCCCombine(SDNode *N, SelectionDAG &DAG) argument 981 performVSELECTCombine(SDNode *N, SelectionDAG &DAG) argument 998 performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument 1027 SelectionDAG &DAG = DCI.DAG; local 1058 N->printrWithDepth(dbgs(), &DAG); dbgs() << "\\n=> \\n"; local 1059 Val.getNode()->printrWithDepth(dbgs(), &DAG); dbgs() << "\\n"); local 1287 initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG) argument 1295 extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG) argument 1313 lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument 1361 lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument 1374 lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) argument 1418 lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned = false) argument 1427 getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG) argument 1463 lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian) argument 1507 truncateVecElts(SDValue Op, SelectionDAG &DAG) argument 1520 lowerMSABitClear(SDValue Op, SelectionDAG &DAG) argument 1530 lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) argument 2293 lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget) argument 2367 lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget) argument 2553 lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2634 isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2666 lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2712 lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2759 lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2806 lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2854 lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2897 lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2933 lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument [all...] |
H A D | MipsSEISelLowering.h | 1 //===- MipsSEISelLowering.h - MipsSE DAG Lowering Interface -----*- C++ -*-===// 48 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 74 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 75 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 76 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 79 SelectionDAG &DAG) const; 81 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 82 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 83 SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 84 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) cons [all...] |
H A D | MipsISelLowering.cpp | 1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===// 10 // selection DAG. 142 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 143 MachineFunction &MF = DAG.getMachineFunction(); 145 return DAG.getRegister(FI->getGlobalBaseReg(MF), Ty); 149 SelectionDAG &DAG, 151 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 155 SelectionDAG &DAG, 157 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 161 SelectionDAG &DAG, 148 getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument 154 getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument 160 getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument 166 getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument 172 getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument 565 performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 642 createFPCmp(SelectionDAG &DAG, const SDValue &Op) argument 664 createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, const SDLoc &DL) argument 674 performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 755 performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 782 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 864 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 1055 performSUBCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 1070 performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 1102 performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 1155 SelectionDAG &DAG = DCI.DAG; local 2316 lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert) argument 2363 lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert) argument 2421 lowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert) argument 2458 lowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert) argument 2596 lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const argument 2647 createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset) argument 2729 createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset) argument 2746 lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle) argument 2775 lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG, bool SingleFloat) argument 3141 SelectionDAG &DAG = CLI.DAG; local 3478 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, TargetLowering::CallLoweringInfo &CLI) const argument 3545 UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, EVT ArgVT, const SDLoc &DL, SelectionDAG &DAG) argument 3605 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 4315 copyByValRegs( SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, MipsCCState &State) const argument 4368 passByValArg( SDValue Chain, const SDLoc &DL, std::deque<std::pair<unsigned, SDValue>> &RegsToPass, SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, const CCValAssign &VA) const argument 4464 writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain, const SDLoc &DL, SelectionDAG &DAG, CCState &State) const argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.h | 1 //===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===// 10 // selection DAG. 24 /// AVR Specific DAG Nodes 98 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 101 SelectionDAG &DAG) const override; 109 SelectionDAG &DAG) const override; 113 SelectionDAG &DAG) const override; 138 SelectionDAG &DAG) const override; 150 SelectionDAG &DAG, SDLoc dl) const; 151 SDValue getAVRCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblySelectionDAGInfo.h | 25 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, 32 EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, 37 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &DL,
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H A D | WebAssemblyISelLowering.cpp | 1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==// 802 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg) { argument 803 MachineFunction &MF = DAG.getMachineFunction(); 804 DAG.getContext()->diagnose( 826 SelectionDAG &DAG = CLI.DAG; local 830 MachineFunction &MF = DAG.getMachineFunction(); 835 fail(DL, DAG, 839 fail(DL, DAG, "WebAssembly doesn't support patch point yet"); 844 fail(DL, DAG, Ms 1112 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1540 getCppExceptionSymNode(SDValue Op, unsigned TagIndex, SelectionDAG &DAG) argument 1975 unrollVectorShift(SDValue Op, SelectionDAG &DAG) argument 2056 auto &DAG = DCI.DAG; local 2081 auto &DAG = DCI.DAG; local 2129 auto &DAG = DCI.DAG; local 2194 auto &DAG = DCI.DAG; local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.h | 23 bool isBaseRegConflictPossible(SelectionDAG &DAG, 29 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, 35 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
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H A D | X86ISelLowering.h | 1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 10 // selection DAG. 24 // X86 Specific DAG Nodes 669 // DAG to CSE everything and decide at isel. 917 SelectionDAG &DAG) const override; 948 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 954 SelectionDAG &DAG) const override; 973 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, 982 /// This method returns the name of a target specific DAG node. 992 const SelectionDAG &DAG) cons [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===// 10 /// Custom DAG lowering for R600 444 // Custom DAG Lowering Operations 447 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 448 MachineFunction &MF = DAG.getMachineFunction(); 451 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 452 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 453 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 456 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 457 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, IS 672 vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const argument 775 LowerUADDSUBO(SDValue Op, SelectionDAG &DAG, unsigned mainop, unsigned ovf) const argument 813 LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL, unsigned DwordOffset) const argument 1489 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1594 CompactSwizzlableVector( SelectionDAG &DAG, SDValue VectorEntry, DenseMap<unsigned, unsigned> &RemapSwizzle) argument 1639 ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry, DenseMap<unsigned, unsigned> &RemapSwizzle) argument 1679 OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4], SelectionDAG &DAG, const SDLoc &DL) const argument 1755 SelectionDAG &DAG = DCI.DAG; local [all...] |
H A D | SIMachineScheduler.cpp | 255 TryCand.IsLowLatency = DAG->IsLowLatencySU[SU->NodeNum]; 256 TryCand.LowLatencyOffset = DAG->LowLatencyOffset[SU->NodeNum]; 310 LiveIntervals *LIS = DAG->getLIS(); 311 MachineRegisterInfo *MRI = DAG->getMRI(); 312 DAG->initRPTracker(TopRPTracker); 313 DAG->initRPTracker(BotRPTracker); 314 DAG->initRPTracker(RPTracker); 454 DAG->dumpNode(*SuccSU); 468 if (SuccSU->NodeNum >= DAG->SUnits.size()) 496 if (DAG 604 SIScheduleBlockCreator(SIScheduleDAGMI *DAG) argument 1422 SIScheduleBlockScheduler(SIScheduleDAGMI *DAG, SISchedulerBlockSchedulerVariant Variant, SIScheduleBlocks BlocksStruct) argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.h | 26 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &DL, 33 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &DL, 40 EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, 46 EmitTargetCodeForMemchr(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, 51 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dest, 56 EmitTargetCodeForStrcmp(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, 62 EmitTargetCodeForStrlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, 67 EmitTargetCodeForStrnlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain,
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 37 LLVM_DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; N->dump(&DAG); 45 N->dump(&DAG); 198 return DAG.getNode(N->getOpcode(), SDLoc(N), 206 return DAG.getNode(N->getOpcode(), SDLoc(N), Op0.getValueType(), Op0, Op1, 214 return DAG.getNode(N->getOpcode(), SDLoc(N), Op0.getValueType(), Op0, Op1, 240 SDValue Result = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(ValueVTs), 261 DAG.ExtractVectorElements(N->getOperand(0), ElemsLHS); 262 DAG.ExtractVectorElements(N->getOperand(1), ElemsRHS); 267 SDVTList ScalarVTs = DAG 3197 CollectOpsToWiden(SelectionDAG &DAG, const TargetLowering &TLI, SmallVectorImpl<SDValue> &ConcatOps, unsigned ConcatEnd, EVT VT, EVT MaxVT, EVT WidenVT) argument 5140 FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, unsigned Width, EVT WidenVT, unsigned Align = 0, unsigned WidenEx = 0) argument 5212 BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, SmallVectorImpl<SDValue> &LdOps, unsigned Start, unsigned End) argument [all...] |
H A D | LegalizeFloatTypes.cpp | 49 LLVM_DEBUG(dbgs() << "Soften float result " << ResNo << ": "; N->dump(&DAG); 57 N->dump(&DAG); dbgs() << "\n"; 158 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 167 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, NVT, Op, 177 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 188 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, NVT, Ops, 201 EVT Ty = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 202 return DAG.getNode(ISD::FREEZE, SDLoc(N), Ty, 214 return DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), 215 TLI.getTypeToTransformTo(*DAG [all...] |
H A D | LegalizeTypes.cpp | 1 //===-- LegalizeTypes.cpp - Common code for DAG type legalizer ------------===// 44 // Note that it is possible to have nodes marked NewNode in the DAG. This can 47 // folding that occurs when using the DAG.getNode operators. Secondly, a new 49 // into a different node, leaving the original node as a NewNode in the DAG. 58 // to live on in the DAG. 59 // The conclusion is that though there may be nodes marked NewNode in the DAG, 71 // over the DAG we never dereference deleted nodes). This means that it may 77 for (SDNode &Node : DAG.allnodes()) { 200 HandleSDNode Dummy(DAG.getRoot()); 205 DAG [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 1 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===// 10 // selection DAG. 988 ISD::CondCode &CC, SelectionDAG &DAG) { 991 RHS = DAG.getConstant(0, DL, RHS.getValueType()); 998 LHS = DAG.getConstant(0, DL, RHS.getValueType()); 1016 // Return the RISC-V branch opcode that matches the given DAG integer 1241 static MVT getContainerForFixedLengthVector(SelectionDAG &DAG, MVT VT, argument 1243 return getContainerForFixedLengthVector(DAG.getTargetLoweringInfo(), VT, 1252 static SDValue convertToScalableVector(EVT VT, SDValue V, SelectionDAG &DAG, argument 1259 SDValue Zero = DAG 987 translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS, ISD::CondCode &CC, SelectionDAG &DAG) argument 1264 convertFromScalableVector(EVT VT, SDValue V, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument 1279 getDefaultVLOps(MVT VecVT, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument 1293 getDefaultScalableVLOps(MVT VecVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument 1320 lowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument 1337 lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument 1610 splatPartsI64ThroughStack(const SDLoc &DL, MVT VT, SDValue Lo, SDValue Hi, SDValue VL, SelectionDAG &DAG) argument 1645 splatPartsI64WithVL(const SDLoc &DL, MVT VT, SDValue Lo, SDValue Hi, SDValue VL, SelectionDAG &DAG) argument 1663 splatSplitI64WithVL(const SDLoc &DL, MVT VT, SDValue Scalar, SDValue VL, SelectionDAG &DAG) argument 1676 lowerScalarSplat(SDValue Scalar, SDValue VL, MVT VT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument 1703 lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument 1896 getRVVFPExtendOrRound(SDValue Op, MVT VT, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument 2443 getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags) argument 2448 getTargetNode(BlockAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags) argument 2454 getTargetNode(ConstantPoolSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags) argument 2460 getTargetNode(JumpTableSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags) argument 2466 getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal) const argument 2549 getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, bool UseGOT) const argument 2845 lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const argument 2974 lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, int64_t ExtTrueVal) const argument 3025 lowerFixedLengthVectorExtendToRVV( SDValue Op, SelectionDAG &DAG, unsigned ExtendOpc) const argument 3244 lowerVectorIntrinsicSplats(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument 3611 getRVVFPReductionOpAndOperands(SDValue Op, SelectionDAG &DAG, EVT EltVT) argument 4187 lowerFixedLengthVectorLogicOpToRVV( SDValue Op, SelectionDAG &DAG, unsigned MaskOpc, unsigned VecOpc) const argument 4269 lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc, bool HasMask) const argument 4308 lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc) const argument 4595 customLegalizeToWOp(SDNode *N, SelectionDAG &DAG, unsigned ExtOpc = ISD::ANY_EXTEND) argument 4608 customLegalizeToWOpWithSExt(SDNode *N, SelectionDAG &DAG) argument 5211 combineORToGREV(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument 5237 combineORToGORC(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument 5316 combineORToSHFL(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) argument 5393 combineGREVI_GORCI(SDNode *N, SelectionDAG &DAG) argument 5430 combineSelectCCAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, SelectionDAG &DAG, bool AllOnes) argument 5467 combineSelectCCAndUseCommutative(SDNode *N, SelectionDAG &DAG, bool AllOnes) argument 5481 SelectionDAG &DAG = DCI.DAG; local 5490 SelectionDAG &DAG = DCI.DAG; local 5508 SelectionDAG &DAG = DCI.DAG; local 5517 SelectionDAG &DAG = DCI.DAG; local 6055 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument 6140 ComputeNumSignBitsForTargetNode( SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument 6960 convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget) argument 6984 unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const RISCVTargetLowering &TLI) argument 7002 convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL, const RISCVSubtarget &Subtarget) argument 7028 unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL) argument 7056 unpackF64OnRV32DSoftABI(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL) argument 7207 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 7433 getPrefTypeAlign(EVT VT, SelectionDAG &DAG) argument 7442 SelectionDAG &DAG = CLI.DAG; local 8524 splitValueIntoRegisterParts( SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const argument 8566 joinRegisterPartsIntoValue( SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 1 //===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===// 10 // selection DAG. 38 static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg) { argument 39 MachineFunction &MF = DAG.getMachineFunction(); 40 DAG.getContext()->diagnose( 44 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg, argument 46 MachineFunction &MF = DAG.getMachineFunction(); 52 DAG.getContext()->diagnose( 258 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const { 278 fail(DL, DAG, err_ms 299 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 370 SelectionDAG &DAG = CLI.DAG; local 547 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.h | 26 const ScheduleDAG *DAG; member in class:llvm::PPCDispatchGroupSBHazardRecognizer 36 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_), 56 const ScheduleDAG &DAG; member in class:llvm::PPCHazardRecognizer970 77 PPCHazardRecognizer970(const ScheduleDAG &DAG);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
H A D | XCoreSelectionDAGInfo.h | 22 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGTargetInfo.h | 51 virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, argument 68 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, 80 virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, argument 93 EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, argument 105 EmitTargetCodeForMemchr(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, argument 118 EmitTargetCodeForStrcpy(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, argument 130 EmitTargetCodeForStrcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, argument 138 EmitTargetCodeForStrlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, argument 144 EmitTargetCodeForStrnlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, argument 150 virtual SDValue EmitTargetCodeForSetTag(SelectionDAG &DAG, cons argument 67 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===// 339 SelectionDAG &DAG) const { 343 case ISD::SRA: return LowerShifts(Op, DAG); 344 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 345 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 346 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 347 case ISD::SETCC: return LowerSETCC(Op, DAG); 348 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 349 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 350 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); 566 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 587 SelectionDAG &DAG = CLI.DAG; local 617 LowerCCCArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 803 LowerCCCCallTo( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 933 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1040 EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) argument [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 1 //===-- NVPTXISelLowering.cpp - NVPTX DAG Lowering Implementation ---------===// 10 // selection DAG. 501 // We have some custom DAG combine patterns for these nodes 1186 SDValue NVPTXTargetLowering::getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, argument 1199 bool Ftz = useF32FTZ(DAG.getMachineFunction()); 1202 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 1203 DAG.getConstant(IID, DL, MVT::i32), Operand); 1227 return DAG.getNode( 1229 DAG.getConstant(Intrinsic::nvvm_rcp_approx_ftz_d, DL, MVT::i32), 1236 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) cons 1408 SelectionDAG &DAG = CLI.DAG; local 2409 getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const argument 2444 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 4319 SelectionDAG &DAG = DCI.DAG; local 4752 ReplaceLoadVector(SDNode *N, SelectionDAG &DAG, SmallVectorImpl<SDValue> &Results) argument 4881 ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG, SmallVectorImpl<SDValue> &Results) argument [all...] |