Searched refs:DAG (Results 126 - 150 of 154) sorted by relevance

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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMips16ISelLowering.cpp1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
414 SelectionDAG &DAG = CLI.DAG; local
415 MachineFunction &MF = DAG.getMachineFunction();
490 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction,
491 getPointerTy(DAG.getDataLayout()));
493 JumpTarget = getAddrGlobal(S, CLI.DL, JumpTarget.getValueType(), DAG,
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp964 /// Insert a newly allocated node into the DAG.
1383 // only legalize if the DAG tells us we must produce legal types.
2367 /// TODO: really we should be making this into the DAG equivalent of
2384 /// TODO: really we should be making this into the DAG equivalent of
4440 SelectionDAG &DAG) {
4442 return DAG.getConstant(0, DL, VT);
4449 SelectionDAG &DAG) {
4459 return DAG.getUNDEF(VT);
4485 SelectionDAG &DAG) {
4501 return DAG
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H A DFunctionLoweringInfo.cpp83 SelectionDAG *DAG) {
89 DA = DAG->getDivergenceAnalysis();
206 TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
82 set(const Function &fn, MachineFunction &mf, SelectionDAG *DAG) argument
H A DScheduleDAGRRList.cpp185 // DAG crawling.
318 // the expansion of custom DAG-to-DAG patterns.
353 /// Schedule - Schedule the DAG using list scheduling.
984 if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
1050 // Now that we are committed to unfolding replace DAG Uses.
1052 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i));
1053 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals - 1),
1603 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()];
1856 SUnit *popFromQueue(std::vector<SUnit *> &Q, SF &Picker, ScheduleDAG *DAG) { argument
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H A DSelectionDAGISel.cpp118 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
701 // Allow creating illegal types during DAG building for the basic block.
711 // Make sure the root of the DAG is up-to-date.
717 // Final step, emit the lowered DAG as machine code.
785 LLVM_DEBUG(dbgs() << "Initial selection DAG: "
798 // Run the DAG combiner in pre-legalize mode.
800 NamedRegionTimer T("combine1", "DAG Combining 1", GroupName,
805 LLVM_DEBUG(dbgs() << "Optimized lowered selection DAG: "
815 // Second step, hack on the DAG until it only uses operations and types that
827 LLVM_DEBUG(dbgs() << "Type-legalized selection DAG
1024 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) argument
2791 MatchStateUpdater(SelectionDAG &DAG, SDNode **NodeToMatch, SmallVectorImpl<std::pair<SDValue, SDNode *>> &RN, SmallVectorImpl<MatchScope> &MS) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h1 //===- llvm/CodeGen/SelectionDAG.h - InstSelection DAG ----------*- C++ -*-===//
203 void checkForCycles(const SelectionDAG *DAG, bool force = false);
206 /// Data Dependence DAG representation suitable for instruction selection.
207 /// This DAG is constructed as the first step of instruction selection in order
230 /// whenever manipulating the DAG.
239 /// The root of the entire DAG.
242 /// A linked list of nodes in the current DAG.
283 /// the DAG can optionally implement this interface. This allows the clients
286 /// A DAGUpdateListener automatically registers itself with DAG when it is
290 SelectionDAG &DAG; member in struct:llvm::SelectionDAG::DAGUpdateListener
317 DAGNodeDeletedListener(SelectionDAG &DAG, std::function<void(SDNode *, SDNode *)> Callback) argument
330 SelectionDAG &DAG; member in class:llvm::SelectionDAG::FlagInserter
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H A DTargetInstrInfo.h1275 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, argument
1375 /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1377 /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1497 const ScheduleDAG *DAG) const;
1503 const ScheduleDAGMI *DAG) const;
1509 const ScheduleDAG *DAG) cons
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp20 // represent loop carried dependences in the DAG as order edges to the Phi
21 // nodes. We also perform several passes over the DAG to eliminate unnecessary
171 // A command line option to enable the CopyToPhi DAG mutation.
175 cl::desc("Enable CopyToPhi DAG Mutation"));
830 /// Update the phi dependences to the DAG because ScheduleDAGInstrs no longer
840 // Iterate over each DAG node.
918 /// Iterate over each DAG node and see if we can change any dependences
1192 /// Swap all the anti dependences in the DAG. That means it is no longer a DAG,
1221 SwingSchedulerDAG *DAG) {
1220 createAdjacencyStructure( SwingSchedulerDAG *DAG) argument
1366 apply(ScheduleDAGInstrs *DAG) argument
2465 multipleIterations(SUnit *SU, SwingSchedulerDAG *DAG) argument
2476 computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int *MinEnd, int *MaxStart, int II, SwingSchedulerDAG *DAG) argument
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H A DTargetInstrInfo.cpp1052 const ScheduleDAG *DAG) const {
1059 const InstrItineraryData *II, const ScheduleDAGMI *DAG) const {
1060 return new ScoreboardHazardRecognizer(II, DAG, "machine-scheduler");
1066 const ScheduleDAG *DAG) const {
1067 return new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp731 /// being extended to be a GPR32, but the incoming DAG might be acting on a
1574 SelectionDAG &DAG; member in class:__anon2142::WidenVector
1577 WidenVector(SelectionDAG &DAG) : DAG(DAG) {} argument
1587 SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, WideTy), 0);
1588 return DAG.getTargetInsertSubreg(AArch64::dsub, DL, WideTy, Undef, V64Reg);
1595 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) { argument
1601 return DAG.getTargetExtractSubreg(AArch64::dsub, SDLoc(V128Reg), NarrowTy,
3311 static SDNode *extractSubReg(SelectionDAG *DAG, EV argument
3338 insertSubReg(SelectionDAG *DAG, EVT VT, SDValue V) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h306 const ScheduleDAG *DAG) const override;
309 const ScheduleDAG *DAG) const override;
H A DPPCInstrInfo.cpp97 /// this target when scheduling the DAG.
100 const ScheduleDAG *DAG) const {
107 return new ScoreboardHazardRecognizer(II, DAG);
110 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
114 /// to use for this target when scheduling the DAG.
117 const ScheduleDAG *DAG) const {
119 DAG->MF.getSubtarget<PPCSubtarget>().getCPUDirective();
123 return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
128 assert(DAG->TII && "No InstrInfo?");
130 return new PPCHazardRecognizer970(*DAG);
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H A DPPCISelDAGToDAG.cpp395 return "PowerPC DAG->DAG Pattern Instruction Selection";
2655 BitPermutationSelector(SelectionDAG *DAG)
2656 : CurDAG(DAG) {}
2751 IntegerCompareEliminator(SelectionDAG *DAG,
2752 PPCDAGToDAGISel *Sel) : CurDAG(DAG), S(Sel) {
4496 static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG,
4964 // In case any misguided DAG-level optimizations form an ADD with a
5811 // We don't do this as a DAG combine because we don't want to do it as nodes
6115 LLVM_DEBUG(dbgs() << "PPC DAG preprocessin
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/netbsd-current/external/apache2/llvm/dist/llvm/utils/vim/syntax/
H A Dllvm.vim239 syn match llvmSpecialComment /\v;\s*CHECK-(NEXT|NOT|DAG|SAME|LABEL|COUNT-\d+):.*$/
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h132 const ScheduleDAG *DAG) const override;
136 const ScheduleDAGMI *DAG) const override;
140 const ScheduleDAG *DAG) const override;
H A DARMBaseInstrInfo.cpp128 const ScheduleDAG *DAG) const {
132 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
134 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
141 const InstrItineraryData *II, const ScheduleDAGMI *DAG) const {
149 if (Subtarget.isCortexM7() && !DAG->hasVRegLiveness())
151 std::make_unique<ARMBankConflictHazardRecognizer>(DAG, 0x4, true));
156 auto BHR = TargetInstrInfo::CreateTargetMIHazardRecognizer(II, DAG);
164 const ScheduleDAG *DAG) const {
170 auto BHR = TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
4813 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h266 const ScheduleDAG *DAG) const override;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrInfo.h402 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
H A DX86InstrInfo.cpp6399 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, argument
6413 MachineFunction &MF = DAG.getMachineFunction();
6455 Load = DAG.getMachineNode(Opc, dl, VT, MVT::Other, AddrOps);
6459 DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
6501 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6519 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6524 DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp74 void dump(const llvm::SelectionDAG *DAG) { argument
79 Base.getNode()->dump(DAG);
86 Index.getNode()->dump(DAG);
367 return "SystemZ DAG->DAG Pattern Instruction Selection";
611 // Insert a node into the DAG at least before Pos. This will reposition
614 // The selection DAG must no longer depend on their uniqueness when this
616 static void insertDAGNode(SelectionDAG *DAG, SDNode *Pos, SDValue N) { argument
620 DAG->RepositionNode(Pos->getIterator(), N.getNode());
1955 LLVM_DEBUG(dbgs() << "SystemZ DAG preprocessin
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp77 static SDNode *packConstantV2I16(const SDNode *N, SelectionDAG &DAG, argument
87 return DAG.getMachineNode(AMDGPU::S_MOV_B32, SL, N->getValueType(0),
88 DAG.getTargetConstant(K, SL, MVT::i32));
94 static SDNode *packNegConstantV2I16(const SDNode *N, SelectionDAG &DAG) { argument
95 return packConstantV2I16(N, DAG, true);
367 "AMDGPU DAG->DAG Pattern Instruction Selection", false, false)
376 "AMDGPU DAG->DAG Pattern Instruction Selection", false, false)
378 /// This pass converts a legalized DAG int
918 getBaseWithOffsetUsingSplitOR(SelectionDAG &DAG, SDValue Addr, SDValue &N0, SDValue &N1) argument
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H A DSIInstrInfo.h1033 const ScheduleDAG *DAG) const override;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1350 SelectionDAG &DAG,
1378 SplatVal = DAG.getTargetConstant(SplatImm, SDLoc(N), XLenVT);
1547 // This pass converts a legalized DAG into a RISCV-specific DAG, ready
1349 selectVSplatSimmHelper(SDValue N, SDValue &SplatVal, SelectionDAG &DAG, const RISCVSubtarget &Subtarget, ValidateFn ValidateImm) argument
/netbsd-current/external/apache2/llvm/dist/llvm/lib/TableGen/
H A DRecord.cpp1357 case DAG: {
1460 case DAG: Result = "!dag"; break;
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/TableGen/
H A DRecord.h865 enum TernaryOp : uint8_t { SUBST, FOREACH, FILTER, IF, DAG, SUBSTR, FIND };
1304 /// (v a, b) - Represent a DAG tree value. DAG inits are required

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