Searched refs:SRA (Results 26 - 35 of 35) sorted by relevance

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/macosx-10.10/llvmCore-3425.0.34/lib/Target/X86/
H A DX86ISelLowering.cpp761 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
999 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1000 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1009 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1017 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1063 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1064 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1113 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1136 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1230 setTargetDAGCombine(ISD::SRA);
[all...]
/macosx-10.10/llvmCore-3425.0.34/lib/Target/MBlaze/
H A DMBlazeISelLowering.cpp323 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp114 case ISD::SRA:
547 case ISD::SRA:
1331 case ISD::SRA:
H A DTargetLowering.cpp1528 case ISD::SRA:
3306 // TODO: For UDIV use SRL instead of SRA.
3308 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3367 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/
H A DARMISelLowering.cpp128 setOperationAction(ISD::SRA, VT, Custom);
546 setTargetDAGCombine(ISD::SRA);
613 setOperationAction(ISD::SRA, MVT::i64, Custom);
3433 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3538 assert((N->getOpcode() == ISD::SRA ||
3548 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3565 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3568 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3576 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
5276 case ISD::SRA
[all...]
H A DARMISelDAGToDAG.cpp2387 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
2522 case ISD::SRA:
/macosx-10.10/llvmCore-3425.0.34/include/llvm/TableGen/
H A DRecord.h875 enum BinaryOp { SHL, SRA, SRL, STRCONCAT, CONCAT, EQ }; enumerator in enum:llvm::BinOpInit::BinaryOp
/macosx-10.10/llvmCore-3425.0.34/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1232 if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCISelLowering.cpp509 case PPCISD::SRA: return "PPCISD::SRA";
4086 "Unexpected SRA!");
4101 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
4102 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5472 case PPCISD::SRA:
/macosx-10.10/llvmCore-3425.0.34/lib/TableGen/
H A DTGParser.cpp938 case tgtok::XSRA: Code = BinOpInit::SRA; Type = IntRecTy::get(); break;

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