| /macosx-10.10/llvmCore-3425.0.34/lib/Target/Mips/ |
| H A D | MipsSubtarget.h | 101 InstrItineraryData InstrItins; member in class:llvm::MipsSubtarget
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| /macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/ |
| H A D | PPCSubtarget.cpp | 61 InstrItins = getInstrItineraryForCPU(CPUName);
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| H A D | PPCTargetMachine.cpp | 46 InstrItins(Subtarget.getInstrItineraryData()) {
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| /macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.h | 40 const InstrItineraryData *InstrItins; member in class:llvm::ScheduleDAGSDNodes
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| H A D | ScheduleDAGSDNodes.cpp | 50 InstrItins(mf.getTarget().getInstrItineraryData()) {}
601 if (!InstrItins || InstrItins->isEmpty()) {
615 SU->Latency += TII->getInstrLatency(InstrItins, N);
631 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
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| H A D | ResourcePriorityQueue.cpp | 45 InstrItins(IS->getTargetLowering().getTargetMachine().getInstrItineraryData())
321 if (Packet.size() >= InstrItins->SchedModel->IssueWidth) {
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| /macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/ |
| H A D | ARMSubtarget.cpp | 112 InstrItins = getInstrItineraryForCPU(CPUString);
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| H A D | ARMTargetMachine.cpp | 48 InstrItins(Subtarget.getInstrItineraryData()) {
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| /macosx-10.10/llvmCore-3425.0.34/lib/Target/Hexagon/ |
| H A D | HexagonTargetMachine.cpp | 77 InstrItins(&Subtarget.getInstrItineraryData()) {
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| /macosx-10.10/llvmCore-3425.0.34/lib/Target/X86/ |
| H A D | X86TargetMachine.cpp | 82 InstrItins(Subtarget.getInstrItineraryData()){
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| H A D | X86Subtarget.cpp | 376 InstrItins = getInstrItineraryForCPU(CPUName);
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| /macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/ |
| H A D | MachineLICM.cpp | 69 const InstrItineraryData *InstrItins; member in class:__anon10233::MachineLICM
329 InstrItins = TM->getInstrItineraryData();
1011 if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg))
1029 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i))
1045 if (!InstrItins || InstrItins->isEmpty())
1059 if (!TII->hasLowDefLatency(InstrItins, &MI, i))
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| H A D | PostRASchedulerList.cpp | 205 const InstrItineraryData *InstrItins = TM.getInstrItineraryData(); local
207 TM.getInstrInfo()->CreateTargetPostRAHazardRecognizer(InstrItins, this);
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| H A D | IfConversion.cpp | 156 const InstrItineraryData *InstrItins; member in class:__anon10214::IfConverter
269 InstrItins = MF.getTarget().getInstrItineraryData();
672 unsigned NumCycles = TII->getInstrLatency(InstrItins, &*I,
1496 unsigned NumCycles = TII->getInstrLatency(InstrItins, &*I, &ExtraPredCost);
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| H A D | TwoAddressInstructionPass.cpp | 67 const InstrItineraryData *InstrItins; member in class:__anon10295::TwoAddressInstructionPass
754 if (TII->getInstrLatency(InstrItins, MI) > 1)
870 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
1364 InstrItins = TM.getInstrItineraryData();
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