Searched refs:xe (Results 276 - 300 of 933) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_sh_mask.h166 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
210 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
258 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
322 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe
352 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe
396 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
458 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
488 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe
634 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
874 #define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe
[all...]
H A Duvd_4_2_sh_mask.h152 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
192 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
234 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
296 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe
318 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe
362 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
424 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
454 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe
600 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
/linux-master/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_sh_mask.h160 #define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
423 #define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe
742 #define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe
1078 #define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
1298 #define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
1391 #define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe
1422 #define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
1469 #define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
1546 #define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
1578 #define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_2_1_0_sh_mask.h38 #define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT 0xe
89 #define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT 0xe
108 #define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe
141 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe
366 #define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe
401 #define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe
441 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe
624 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe
720 #define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT 0xe
771 #define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT 0xe
[all...]
H A Ddpcs_4_2_0_sh_mask.h107 #define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
277 #define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
423 #define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe
472 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe
685 #define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe
720 #define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe
760 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe
945 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe
1036 #define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe
1085 #define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe
[all...]
H A Ddpcs_4_2_2_sh_mask.h94 #define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
266 #define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
414 #define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe
463 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe
691 #define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe
726 #define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe
766 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe
951 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe
1053 #define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe
1102 #define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_5_0_0_sh_mask.h48 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
93 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
148 #define AVM_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
213 #define EFC_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
278 #define ENT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
343 #define IME_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
408 #define PPU_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
473 #define SAOE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
538 #define SCM_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
603 #define SDB_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
[all...]
H A Dvcn_4_0_3_sh_mask.h48 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
93 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
148 #define AVM_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
213 #define CDEFE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
278 #define EFC_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
343 #define ENT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
408 #define IME_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
473 #define PPU_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
538 #define SAOE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
603 #define SCM_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_2_sh_mask.h88 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
118 #define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD__SHIFT 0xe
164 #define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe
278 #define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe
362 #define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe
446 #define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe
650 #define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe
668 #define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe
734 #define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe
782 #define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_8_0_sh_mask.h1684 #define DAGB0_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xe
3437 #define DAGB1_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xe
5184 #define DAGB2_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xe
6931 #define DAGB3_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xe
8678 #define DAGB4_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xe
8789 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
8822 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
8855 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
8888 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
9089 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_sh_mask.h73 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
85 #define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
329 #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
341 #define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
562 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
574 #define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
818 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
830 #define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
1107 #define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe
1226 #define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
[all...]
H A Dgc_9_4_3_sh_mask.h50 #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
98 #define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
114 #define GRBM_STATUS__TA_BUSY__SHIFT 0xe
518 #define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe
637 #define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
681 #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
834 #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
868 #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
905 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
961 #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
[all...]
H A Dgc_10_1_0_sh_mask.h207 #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
262 #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
394 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
440 #define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe
478 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0xe
533 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0xe
646 #define SDMA0_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe
681 #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
773 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe
2973 #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_4_3_0_sh_mask.h468 #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
1093 #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
1307 #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe
1406 #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe
1553 #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
1591 #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
1788 #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
1936 #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
2081 #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
2146 #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/hdp/
H A Dhdp_4_4_2_sh_mask.h125 #define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe
156 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0xe
225 #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
460 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe
476 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
634 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe
/linux-master/drivers/video/fbdev/
H A Dplatinumfb.h190 0x56, 0x1e6, 0x206, 0x534, 0x532, 0xa, 0xe, 0x38,
273 0, 0xa5, 0xc3, 0xe, 0x185, 0x1c, 0x1f, 0x30,
309 0, 0xa5, 0xc3, 0xe, 0x185, 0x1c, 0x1f, 0x30,
/linux-master/drivers/ata/pata_parport/
H A Dfrpw.c23 #define cec4 w2(0xc);w2(0xe);w2(0xe);w2(0xc);w2(4);w2(4);w2(4);
206 w2(0xc); w2(0xe); w2(4);
/linux-master/drivers/gpu/drm/i2c/
H A Dsil164_drv.c98 #define SIL164_PLLZONE 0xe
144 for (i = 0x8; i <= 0xe; i++)
153 for (i = 0x8; i <= 0xe; i++)
/linux-master/drivers/tty/vt/
H A Dselection.c341 v->xe = min_t(u16, v->xe - 1, vc->vc_cols - 1);
351 pe = v->ye * vc->vc_size_row + (v->xe << 1);
/linux-master/drivers/gpu/drm/xe/
H A Dxe_gt_sriov_pf_policy.c41 struct xe_device *xe = tile_to_xe(tile); local
46 bo = xe_bo_create_pin_map(xe, tile, NULL,
54 xe_map_memcpy_to(xe, &bo->vmap, 0, klvs, bytes);
H A Dxe_sched_job.c314 struct xe_device *xe = q->gt->tile->xe; local
325 snapshot->batch_addr[i] = xe_device_uncanonicalize_addr(xe, job->batch_addr[i]);
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_sh_mask.h302 #define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
338 #define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
374 #define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
410 #define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
446 #define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
482 #define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
518 #define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
554 #define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
690 #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
708 #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
[all...]
H A Dgfx_8_0_enum.h77 BLEND_ONE_MINUS_CONSTANT_COLOR = 0xe,
117 CMASK_CLR11_F2 = 0xe,
140 CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0xe,
590 CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0xe,
641 CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0xe,
663 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0xe,
764 STENCIL_NOR = 0xe,
794 DB_PERF_SEL_DB_SC_tile_tiles = 0xe,
1081 GRBM_PERF_SEL_CB_CLEAN = 0xe,
1117 GRBM_SE0_PERF_SEL_BCI_BUSY = 0xe,
[all...]
/linux-master/arch/sparc/include/asm/
H A Dpcic.h100 #define PCI_ISIZE_32M 0xe
/linux-master/drivers/scsi/aic7xxx/aicasm/
H A Daicasm_insformat.h190 #define AIC_OP_JE 0xe

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