Searched refs:x1 (Results 501 - 525 of 5699) sorted by relevance

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/linux-master/drivers/phy/rockchip/
H A Dphy-rockchip-emmc.c36 #define PHYCTRL_PDB_MASK 0x1
38 #define PHYCTRL_PDB_PWR_ON 0x1
40 #define PHYCTRL_ENDLL_MASK 0x1
41 #define PHYCTRL_ENDLL_SHIFT 0x1
42 #define PHYCTRL_ENDLL_ENABLE 0x1
44 #define PHYCTRL_CALDONE_MASK 0x1
46 #define PHYCTRL_CALDONE_DONE 0x1
48 #define PHYCTRL_DLLRDY_MASK 0x1
50 #define PHYCTRL_DLLRDY_DONE 0x1
53 #define PHYCTRL_FREQSEL_50M 0x1
[all...]
/linux-master/sound/soc/codecs/
H A Dwm8711.c113 {18432000, 48000, 384, 0x0, 0x1, 0x0},
114 {12000000, 48000, 250, 0x0, 0x0, 0x1},
118 {18432000, 32000, 576, 0x6, 0x1, 0x0},
119 {12000000, 32000, 375, 0x6, 0x0, 0x1},
123 {18432000, 8000, 2304, 0x3, 0x1, 0x0},
125 {16934400, 8000, 2112, 0xb, 0x1, 0x0},
126 {12000000, 8000, 1500, 0x3, 0x0, 0x1},
130 {18432000, 96000, 192, 0x7, 0x1, 0x0},
131 {12000000, 96000, 125, 0x7, 0x0, 0x1},
135 {16934400, 44100, 384, 0x8, 0x1,
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_enum.h47 #define SMC_MSG_TEST 0x1
79 ENDIAN_8IN16 = 0x1,
85 ARRAY_LINEAR_ALIGNED = 0x1,
103 CONFIG_2_PIPE = 0x1,
109 CONFIG_8_BANK = 0x1,
113 CONFIG_512B_GROUP = 0x1,
117 CONFIG_2KB_ROW = 0x1,
127 CONFIG_256B_SWAPS = 0x1,
133 CONFIG_2KB_SPLIT = 0x1,
139 ADDR_CONFIG_2_PIPE = 0x1,
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
41 #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1
43 #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1
55 #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1
57 #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1
69 #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x1
71 #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x1
83 #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x1
85 #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x1
[all...]
H A Ddce_11_2_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
41 #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1
43 #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1
55 #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1
57 #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1
69 #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x1
71 #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x1
83 #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x1
85 #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x1
[all...]
H A Ddce_11_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
41 #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1
43 #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1
55 #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1
57 #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1
69 #define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON_MASK 0x1
71 #define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE_MASK 0x1
83 #define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1
86 #define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1
[all...]
/linux-master/include/linux/qed/
H A Dstorage_common.h97 #define SCSI_INIT_FUNC_QUEUES_RQ_VALID_MASK 0x1
99 #define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_MASK 0x1
101 #define SCSI_INIT_FUNC_QUEUES_CMD_VALID_MASK 0x1
103 #define SCSI_INIT_FUNC_QUEUES_TQ_VALID_MASK 0x1
105 #define SCSI_INIT_FUNC_QUEUES_SOC_EN_MASK 0x1
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
H A Dg84.c39 return (nvkm_rd32(device, 0x00154c) & 0x1) + 1;
46 nvkm_mask(device, 0x00154c, 0x1, (ver >= 2 ? 0x1 : 0x0));
91 nvkm_pci_mask(pci, 0x460, 0x1, 0x1);
/linux-master/drivers/media/platform/qcom/venus/
H A Dhfi_venus_io.h31 #define VIDC_CTRL_INIT_CTRL_MASK 0x1
39 #define CPU_CS_SCIACMDARG0_ERROR_STATUS_SHIFT 0x1
40 #define CPU_CS_SCIACMDARG0_INIT_STATUS_MASK 0x1
62 #define CPU_CS_X2RPMH_MASK0_BMSK_V6 0x1
65 #define CPU_CS_X2RPMH_MASK1_SHFT_V6 0x1
/linux-master/arch/arm/mach-mvebu/
H A Dsystem-controller.c54 .rstoutn_mask_reset_out_en = 0x1,
55 .system_soft_reset = 0x1,
63 .rstoutn_mask_reset_out_en = 0x1,
64 .system_soft_reset = 0x1,
74 .system_soft_reset = 0x1,
/linux-master/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Darc_farm_arc0_aux_masks.h25 #define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_MASK 0x1
31 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_MASK 0x1
51 #define ARC_FARM_ARC0_AUX_DBG_MODE_DBG_PROT_SEL_MASK 0x1
71 #define ARC_FARM_ARC0_AUX_WAKE_UP_EVENT_VAL_MASK 0x1
83 #define ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL_RUN_HALT_MASK 0x1
87 #define ARC_FARM_ARC0_AUX_ARC_RST_CORE_MASK 0x1
93 #define ARC_FARM_ARC0_AUX_ARC_RST_REQ_VAL_MASK 0x1
221 #define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_INTR_EN_MASK 0x1
235 #define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_SERR_MASK 0x1
401 #define ARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN_CBU_VAL_MASK 0x1
[all...]
/linux-master/arch/m68k/coldfire/
H A Dintc.c49 __raw_writew(imr | (0x1 << index), MCFSIM_IMR);
56 __raw_writew(imr & ~(0x1 << index), MCFSIM_IMR);
73 __raw_writel(imr | (0x1 << index), MCFSIM_IMR);
80 __raw_writel(imr & ~(0x1 << index), MCFSIM_IMR);
108 avec |= (0x1 << (irq - EIRQ1 + 1));
/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_0_ppsmc.h27 #define PPSMC_VERSION 0x1
28 #define DEBUGSMC_VERSION 0x1
31 #define PPSMC_Result_OK 0x1
39 #define PPSMC_MSG_TestMessage 0x1
146 #define DEBUGSMC_MSG_TestMessage 0x1
/linux-master/drivers/pinctrl/
H A Dpinctrl-keembay.c141 KEEMBAY_MUX(0x1, "SD0_M1"),
150 KEEMBAY_MUX(0x1, "SD0_M1"),
159 KEEMBAY_MUX(0x1, "I2S0_M1"),
168 KEEMBAY_MUX(0x1, "I2S0_M1"),
177 KEEMBAY_MUX(0x1, "I2S0_M1"),
186 KEEMBAY_MUX(0x1, "I2S0_M1"),
195 KEEMBAY_MUX(0x1, "SD0_M1"),
204 KEEMBAY_MUX(0x1, "SD0_M1"),
213 KEEMBAY_MUX(0x1, "I2S1_M1"),
222 KEEMBAY_MUX(0x1, "I2S1_M
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h41 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1
44 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
51 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
54 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
121 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1
124 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
135 #define UVD_CGC_GATE__SYS_MASK 0x1
138 #define UVD_CGC_GATE__UDEC__SHIFT 0x1
179 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1
182 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1
[all...]
H A Duvd_6_0_sh_mask.h41 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1
44 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
51 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
54 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
123 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1
126 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
137 #define UVD_CGC_GATE__SYS_MASK 0x1
140 #define UVD_CGC_GATE__UDEC__SHIFT 0x1
181 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1
184 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1
[all...]
/linux-master/sound/ppc/
H A Dsnd_ps3_reg.h236 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY2 (0x1 << 12) /* RW--V */
246 #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY2 (0x1 << 16) /* RW--V */
251 #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY2 (0x1 << 20) /* RW--V */
347 #define PS3_AUDIO_AO_MCTRL_MCLKC1_ENABLED (0x1 << 12) /* RW--V */
362 #define PS3_AUDIO_AO_MCTRL_MCLKC0_ENABLED (0x1 << 14) /* RW--V */
469 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV2 (0x1 << 20) /* RWI-V */
545 #define PS3_AUDIO_AO_3WCTRL_ASODB_RESVD (0x1 << 8) /* RWI-V */
594 #define PS3_AUDIO_AO_SPDCTRL_SPODB_RESVD (0x1 << 8) /* RW--V */
618 #define PS3_AUDIO_AO_SPDCTRL_SPOSS_SPDIF (0x1 << 16) /* RW--V */
626 #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV2 (0x1 << 2
[all...]
/linux-master/crypto/
H A Dseed.c333 u32 i, t0, t1, x1, x2, x3, x4; local
335 x1 = be32_to_cpu(key[0]);
341 t0 = x1 + x3 - KC[i];
349 t0 = x1;
350 x1 = (x1 >> 8) ^ (x2 << 24);
369 u32 x1, x2, x3, x4, t0, t1; local
372 x1 = be32_to_cpu(src[0]);
377 OP(x1, x2, x3, x4, 0);
378 OP(x3, x4, x1, x
407 u32 x1, x2, x3, x4, t0, t1; local
[all...]
/linux-master/drivers/dma/ioat/
H A Dregisters.h99 #define IOAT_CHANSTS_DONE 0x1
119 #define IOAT_DCA_COMP_V1 0x1
122 #define IOAT_FSB_CAPABILITY_PREFETCH 0x1
125 #define IOAT_PCI_CAPABILITY_MEMWR 0x1
128 #define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1
131 #define IOAT_PCI_CAP_ENABLE_MEMWR 0x1
154 #define IOAT3_CSI_CAPABILITY_PREFETCH 0x1
157 #define IOAT3_PCI_CAPABILITY_MEMWR 0x1
160 #define IOAT3_CSI_CONTROL_PREFETCH 0x1
163 #define IOAT3_PCI_CONTROL_MEMWR 0x1
[all...]
/linux-master/drivers/net/hamradio/
H A Dz8530.h39 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
56 #define RxENABLE 0x1 /* Rx Enable */
69 #define PAR_ENA 0x1 /* Parity Enable */
82 #define X1CLK 0x0 /* x1 clock mode */
89 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
173 #define Rx_CH_AV 0x1 /* Rx Character Available */
183 #define ALL_SNT 0x1 /* All sent */
202 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
/linux-master/drivers/tty/serial/
H A Dzs.h91 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
108 #define RxENABLE 0x1 /* Rx Enable */
121 #define PAR_ENA 0x1 /* Parity Enable */
135 #define X1CLK 0x0 /* x1 clock mode */
142 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
229 #define Rx_CH_AV 0x1 /* Rx Character Available */
239 #define ALL_SNT 0x1 /* All sent */
260 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
/linux-master/drivers/scsi/qedf/
H A Dqedf_hsi.h54 #define FCOE_CMDQE_CONTROL_ABTSREQCMD_MASK 0x1
77 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_MASK 0x1
79 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_MASK 0x1
81 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_MASK 0x1
83 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_MASK 0x1
85 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_MASK 0x1
103 #define FCOE_CQE_RSP_INFO_FW_UNDERRUN_MASK 0x1 /* FW detected underrun */
196 * 0x1 - Indicating on an unsolicited event notification. use enum
/linux-master/include/linux/mfd/
H A Dwl1273-core.h158 #define WL1273_IS2_WIDTH_40 0x1
171 #define WL1273_IS2_FORMAT_LEFT (0x1 << 4)
176 #define WL1273_IS2_SLAVEW (0x1 << 6)
179 #define WL1273_IS2_TRI_ALWAYS_ACTIVE (0x1 << 7)
182 #define WL1273_IS2_SDOWS_RF (0x1 << 8)
187 #define WL1273_IS2_TRI_ALWAYS (0x1 << 10)
190 #define WL1273_IS2_RATE_44_1K (0x1 << 12)
/linux-master/drivers/net/ethernet/huawei/hinic/
H A Dhinic_hw_api_cmd.h29 #define HINIC_API_CMD_CHAIN_REQ_RESTART_MASK 0x1
50 #define HINIC_API_CMD_CHAIN_CTRL_RESTART_WB_STAT_MASK 0x1
51 #define HINIC_API_CMD_CHAIN_CTRL_XOR_ERR_MASK 0x1
52 #define HINIC_API_CMD_CHAIN_CTRL_AEQE_EN_MASK 0x1
86 #define HINIC_API_CMD_DESC_API_TYPE_MASK 0x1
87 #define HINIC_API_CMD_DESC_RD_WR_MASK 0x1
88 #define HINIC_API_CMD_DESC_MGMT_BYPASS_MASK 0x1
/linux-master/drivers/scsi/lpfc/
H A Dlpfc_disc.h81 NLP_XPT_REGD = 0x1,
90 NLP_IN_RECOV_POST_DEV_LOSS = 0x1,
107 #define NLP_FC_NODE 0x1 /* entry is an FC node */
121 #define NLP_FC4_FCP 0x1 /* FC4 Type FCP (value x8)) */
137 #define NLP_NVME_NSLER 0x1 /* NVME NSLER device */
227 #define NLP_STE_PLOGI_ISSUE 0x1 /* PLOGI was sent to NL_PORT */
280 #define NLP_EVT_RCV_PRLI 0x1 /* Rcv'd an ELS PRLI command */

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