Searched refs:x1 (Results 251 - 275 of 5700) sorted by relevance

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/linux-master/arch/arm/mach-s3c/
H A Dregs-gpio-s3c64xx.h44 #define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30)
51 #define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28)
58 #define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26)
65 #define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24)
72 #define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22)
81 #define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18)
88 #define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16)
94 #define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14)
100 #define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12)
106 #define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 <<
[all...]
/linux-master/tools/testing/selftests/arm64/fp/
H A Dasm-utils.S16 mov x1, sp
29 mov x1, x0
48 mov x1, sp
52 strb w2, [x1, #-1]! // Write the NUL terminator
58 strb w0, [x1, #-1]!
62 ldrb w0, [x1]
65 strb w0, [x1, #-1]!
67 1: mov x0, x1
113 // x0=data in, x1=size in, clobbers x0-x5,x8
118 mov x5, x1
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/linux-master/arch/arm/boot/dts/nxp/imx/
H A Dimx6sl-pinfunc.h14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
29 #define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI 0x054 0x2ac 0x6bc 0x1 0x0
36 #define MX6SL_PAD_AUD_RXFS__I2C1_SCL 0x058 0x2b0 0x71c 0x1 0x0
37 #define MX6SL_PAD_AUD_RXFS__UART3_RX_DATA 0x058 0x2b0 0x80c 0x2 0x1
44 #define MX6SL_PAD_AUD_TXC__ECSPI3_MISO 0x05c 0x2b4 0x6b8 0x1 0x0
46 #define MX6SL_PAD_AUD_TXC__UART4_RX_DATA 0x05c 0x2b4 0x814 0x2 0x1
51 #define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK 0x060 0x2b8 0x6b0 0x1 0x0
58 #define MX6SL_PAD_AUD_TXFS__PWM3_OUT 0x064 0x2bc 0x000 0x1 0x0
59 #define MX6SL_PAD_AUD_TXFS__UART4_RTS_B 0x064 0x2bc 0x810 0x2 0x1
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H A Dimx51-pinfunc.h16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
28 #define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0
30 #define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1
35 #define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0
37 #define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1
41 #define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0
46 #define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0
51 #define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0
55 #define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1
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H A Dimx7d-pinfunc.h15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
26 #define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
33 #define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
40 #define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
41 #define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
47 #define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
48 #define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
54 #define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1
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H A Dimx6q-pinfunc.h14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
26 #define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0
32 #define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0
37 #define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0
40 #define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0
43 #define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0
46 #define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0
49 #define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0
52 #define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1
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/linux-master/scripts/dtc/include-prefixes/arm/nxp/imx/
H A Dimx6sl-pinfunc.h14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
29 #define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI 0x054 0x2ac 0x6bc 0x1 0x0
36 #define MX6SL_PAD_AUD_RXFS__I2C1_SCL 0x058 0x2b0 0x71c 0x1 0x0
37 #define MX6SL_PAD_AUD_RXFS__UART3_RX_DATA 0x058 0x2b0 0x80c 0x2 0x1
44 #define MX6SL_PAD_AUD_TXC__ECSPI3_MISO 0x05c 0x2b4 0x6b8 0x1 0x0
46 #define MX6SL_PAD_AUD_TXC__UART4_RX_DATA 0x05c 0x2b4 0x814 0x2 0x1
51 #define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK 0x060 0x2b8 0x6b0 0x1 0x0
58 #define MX6SL_PAD_AUD_TXFS__PWM3_OUT 0x064 0x2bc 0x000 0x1 0x0
59 #define MX6SL_PAD_AUD_TXFS__UART4_RTS_B 0x064 0x2bc 0x810 0x2 0x1
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H A Dimx51-pinfunc.h16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
28 #define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0
30 #define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1
35 #define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0
37 #define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1
41 #define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0
46 #define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0
51 #define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0
55 #define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1
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H A Dimx7d-pinfunc.h15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
26 #define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
33 #define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
40 #define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
41 #define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
47 #define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
48 #define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
54 #define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1
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H A Dimx6q-pinfunc.h14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
26 #define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0
32 #define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0
37 #define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0
40 #define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0
43 #define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0
46 #define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0
49 #define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0
52 #define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1
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/linux-master/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c221 [0x1] = "CCPLEX_DPMU",
278 [0x1] = "ape_p2ps/I/ape_p2ps",
297 [0x1] = "axis_satellite_axi2apb_p2pm/T/axis_satellite_axi2apb_p2pm",
322 { 0x0, 0x1, 0x00, 0x0, 0x02003000, 0, 0x02003000 },
323 { 0x0, 0x1, 0x01, 0x0, 0x02006000, 2, 0x02006000 },
324 { 0x0, 0x1, 0x02, 0x0, 0x02016000, 3, 0x02016000 },
325 { 0x0, 0x1, 0x03, 0x0, 0x0201d000, 4, 0x0201d000 },
326 { 0x0, 0x1, 0x04, 0x0, 0x0202b000, 6, 0x0202b000 },
327 { 0x0, 0x1, 0x05, 0x0, 0x02434000, 20, 0x02434000 },
328 { 0x0, 0x1,
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/linux-master/arch/arm64/kernel/
H A Dhibernate-asm.S41 * x1: physical address of swapper page tables
55 mov x21, x1
65 ldr x1, [x19, #HIBERN_PBE_ADDR]
67 copy_page x0, x1, x2, x3, x4, x5, x6, x7, x8, x9
69 add x1, x10, #PAGE_SIZE
77 cmp x4, x1
/linux-master/drivers/soc/mediatek/
H A Dmt8365-mmsys.h17 #define MT8365_RDMA0_SOUT_COLOR0 0x1
18 #define MT8365_DITHER_MOUT_EN_DSI0 0x1
19 #define MT8365_DSI0_SEL_IN_DITHER 0x1
24 #define MT8365_RDMA1_SOUT_DPI0 0x1
26 #define MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK 0x1
H A Dmtk-mmsys.h26 #define OVL0_MOUT_EN_COLOR0 0x1
27 #define OD_MOUT_EN_RDMA0 0x1
29 #define UFOE_MOUT_EN_DSI0 0x1
30 #define COLOR0_SEL_IN_OVL0 0x1
31 #define OVL1_MOUT_EN_COLOR1 0x1
32 #define GAMMA_MOUT_EN_RDMA1 0x1
35 #define RDMA0_SOUT_DSI1 0x1
41 #define RDMA1_SOUT_DSI1 0x1
47 #define RDMA2_SOUT_DSI1 0x1
51 #define DPI0_SEL_IN_RDMA1 0x1
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/linux-master/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_sync_mngr_glbl_masks.h25 #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_SO_OVERFLOW_MASK 0x1
77 #define DCORE0_SYNC_MNGR_GLBL_SOB_ONLY_EN_MASK 0x1
81 #define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK 0x1
115 #define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_SEC_MASK 0x1
133 #define DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_MODE_MASK 0x1
H A Dpdma0_core_special_masks.h51 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_INJ_MASK 0x1
61 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_SERR_MASK 0x1
67 #define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_MASK 0x1
89 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_MASK 0x1
111 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK 0x1
/linux-master/sound/soc/uniphier/
H A Daio-reg.h51 #define A2AIOINPUTSEL_RXSEL_PCMI3_EVEA (0x1 << 8)
69 #define IPORTMXCTR1_LRSEL_LEFT (0x1 << 10)
78 #define IPORTMXCTR1_CHSEL_D0_D2 (0x1 << 4)
85 #define IPORTMXCTR1_FSSEL_96 (0x1 << 0)
100 #define IPORTMXCTR2_ACLKSEL_F1 (0x1 << 16)
108 #define IPORTMXCTR2_MSSEL_MASTER (0x1 << 15)
111 #define IPORTMXCTR2_EXTLSIFSSEL_24 (0x1 << 14)
114 #define IPORTMXCTR2_DACCKSEL_1_3 (0x1 << 8)
119 #define IPORTMXCTR2_REQEN_ENABLE (0x1 << 0)
130 #define IPORTMXEXNOE_PCMINOE_INPUT (0x1 <<
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/linux-master/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
27 #define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x020 0x280 0x000 0x1 0x0
31 #define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x024 0x284 0x000 0x1 0x0
35 #define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 0x028 0x288 0x000 0x1 0x0
39 #define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 0x02C 0x28C 0x000 0x1 0x0
44 #define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 0x030 0x290 0x590 0x1 0x0
49 #define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN 0x034 0x294 0x000 0x1 0x0
55 #define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x038 0x298 0x000 0x1
[all...]
/linux-master/scripts/dtc/include-prefixes/arm64/freescale/
H A Dimx8mp-pinfunc.h14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
27 #define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x020 0x280 0x000 0x1 0x0
31 #define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x024 0x284 0x000 0x1 0x0
35 #define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 0x028 0x288 0x000 0x1 0x0
39 #define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 0x02C 0x28C 0x000 0x1 0x0
44 #define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 0x030 0x290 0x590 0x1 0x0
49 #define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN 0x034 0x294 0x000 0x1 0x0
55 #define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x038 0x298 0x000 0x1
[all...]
/linux-master/drivers/pinctrl/mvebu/
H A Dpinctrl-kirkwood.c37 MPP_VAR_FUNCTION(0x1, "nand", "io2", V(1, 1, 1, 1, 1, 1, 1)),
41 MPP_VAR_FUNCTION(0x1, "nand", "io3", V(1, 1, 1, 1, 1, 1, 1)),
45 MPP_VAR_FUNCTION(0x1, "nand", "io4", V(1, 1, 1, 1, 1, 1, 1)),
49 MPP_VAR_FUNCTION(0x1, "nand", "io5", V(1, 1, 1, 1, 1, 1, 1)),
53 MPP_VAR_FUNCTION(0x1, "nand", "io6", V(1, 1, 1, 1, 1, 1, 1)),
60 MPP_VAR_FUNCTION(0x1, "nand", "io7", V(1, 1, 1, 1, 1, 1, 1)),
66 MPP_VAR_FUNCTION(0x1, "sysrst", "out", V(1, 1, 1, 1, 1, 1, 1)),
71 MPP_VAR_FUNCTION(0x1, "pex", "rsto", V(1, 1, 1, 1, 0, 1, 1)),
77 MPP_VAR_FUNCTION(0x1, "twsi0", "sda", V(1, 1, 1, 1, 1, 1, 1)),
86 MPP_VAR_FUNCTION(0x1, "twsi
[all...]
/linux-master/arch/mips/include/asm/
H A Dmsa.h238 #define MSA_IR_WRPF (_ULCAST_(0x1) << MSA_IR_WRPB)
250 #define MSA_CSR_FLAGS_IF (_ULCAST_(0x1) << MSA_CSR_FLAGS_IB)
252 #define MSA_CSR_FLAGS_UF (_ULCAST_(0x1) << MSA_CSR_FLAGS_UB)
254 #define MSA_CSR_FLAGS_OF (_ULCAST_(0x1) << MSA_CSR_FLAGS_OB)
256 #define MSA_CSR_FLAGS_ZF (_ULCAST_(0x1) << MSA_CSR_FLAGS_ZB)
258 #define MSA_CSR_FLAGS_VF (_ULCAST_(0x1) << MSA_CSR_FLAGS_VB)
262 #define MSA_CSR_ENABLES_IF (_ULCAST_(0x1) << MSA_CSR_ENABLES_IB)
264 #define MSA_CSR_ENABLES_UF (_ULCAST_(0x1) << MSA_CSR_ENABLES_UB)
266 #define MSA_CSR_ENABLES_OF (_ULCAST_(0x1) << MSA_CSR_ENABLES_OB)
268 #define MSA_CSR_ENABLES_ZF (_ULCAST_(0x1) << MSA_CSR_ENABLES_Z
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/linux-master/sound/soc/codecs/
H A Drt711-sdca.h116 #define RT711_DAC_DC_CALI_TRIGGER (0x1 << 15)
117 #define RT711_DAC_DC_CALI_CLK_EN (0x1 << 14)
118 #define RT711_DAC_DC_FORCE_CALI_RST (0x1 << 3)
121 #define RT711_JD2_DIGITAL_MODE_SEL (0x1 << 1)
124 #define RT711_JD2_2PORT_200K_DECODE_HP (0x1 << 13)
125 #define RT711_JD2_2PORT_100K_DECODE_MASK (0x1 << 12)
128 #define RT711_HP_JD_SEL_JD2 (0x1 << 1)
131 #define RT711_HP_JD_FINAL_RESULT_CTL_JD12 (0x1 << 10)
133 #define RT711_POW_CC1_AGPI (0x1 << 5)
134 #define RT711_POW_CC1_AGPI_ON (0x1 <<
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/linux-master/arch/arm/mach-orion5x/
H A Dmpp.h66 #define MPP8_GIGE MPP(8, 0x1, 0, 0, 1, 1, 1)
70 #define MPP9_GIGE MPP(9, 0x1, 0, 0, 1, 1, 1)
74 #define MPP10_GIGE MPP(10, 0x1, 0, 0, 1, 1, 1)
78 #define MPP11_GIGE MPP(11, 0x1, 0, 0, 1, 1, 1)
82 #define MPP12_GIGE MPP(12, 0x1, 0, 0, 1, 1, 1)
88 #define MPP13_GIGE MPP(13, 0x1, 0, 0, 1, 1, 1)
94 #define MPP14_GIGE MPP(14, 0x1, 0, 0, 1, 1, 1)
100 #define MPP15_GIGE MPP(15, 0x1, 0, 0, 1, 1, 1)
106 #define MPP16_GIGE MPP(16, 0x1, 0, 0, 1, 1, 1)
112 #define MPP17_GIGE MPP(17, 0x1,
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/linux-master/arch/sh/kernel/vsyscall/
H A Dvsyscall-trapa.S18 .byte 0x1 /* Version number */
20 .uleb128 0x1 /* Code alignment factor */
23 .uleb128 0x1 /* Augmentation length and data */
/linux-master/drivers/gpu/host1x/hw/
H A Dhw_host1x04_channel.h50 return (r >> 11) & 0x1;
92 return (r >> 0) & 0x1;
116 return (v & 0x1) << 2;

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